VERSION = 2
PATCHLEVEL = 6
- SUBLEVEL = 27
- EXTRAVERSION =
- NAME = Rotary Wombat
+ SUBLEVEL = 28
+ EXTRAVERSION = -rc2
+ NAME = Killer Bat of Doom
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
# o print "Entering directory ...";
MAKEFLAGS += -rR --no-print-directory
+# Add custom flags here to avoid conflict with updates
+EXTRAVERSION := $(EXTRAVERSION)-omap1
+
# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
#
-e s/ppc.*/powerpc/ -e s/mips.*/mips/ \
-e s/sh.*/sh/ )
+SUBARCH := arm
+
# Cross compiling and selecting different set of gcc/bin-utils
# ---------------------------------------------------------------------------
#
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
export KBUILD_BUILDHOST := $(SUBARCH)
ARCH ?= $(SUBARCH)
-CROSS_COMPILE ?=
+CROSS_COMPILE ?= arm-linux-
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)
# KBUILD_DEFCONFIG may point out an alternative default configuration
# used for 'make defconfig'
include $(srctree)/arch/$(SRCARCH)/Makefile
- export KBUILD_DEFCONFIG
+ export KBUILD_DEFCONFIG KBUILD_KCONFIG
config %config: scripts_basic outputmakefile FORCE
$(Q)mkdir -p include/linux include/config
config ARM
bool
default y
+ select HAVE_AOUT
select HAVE_IDE
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
bool
default y
- config ARCH_SUPPORTS_AOUT
- def_bool y
-
config ARCH_MAY_HAVE_PC_FDC
bool
config ZONE_DMA
bool
- default y
config GENERIC_ISA_DMA
bool
config OPROFILE_ARM11_CORE
bool
+ config OPROFILE_ARMV7
+ def_bool y
+ depends on CPU_V7 && !SMP
+ bool
+
endif
config VECTORS_BASE
source "init/Kconfig"
+ source "kernel/Kconfig.freezer"
+
menu "System Type"
choice
select TIMER_ACORN
select ISA
select NO_IOPORT
+ select ARCH_SPARSEMEM_ENABLE
help
Support for the Cirrus Logic PS7500FE system-on-a-chip.
select PLAT_IOP
select PCI
select ARCH_SUPPORTS_MSI
+ select VMSPLIT_1G
help
Support for Intel's IOP13XX (XScale) family of processors.
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
+ select DMABOUNCE if PCI
help
Support for Intel's IXP4XX (XScale) family of processors.
help
Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
- Orion-2 (5281).
+ Orion-2 (5281), Orion-1-90 (6183).
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select HAVE_PATA_PLATFORM
select ISA_DMA_API
select NO_IOPORT
+ select ARCH_SPARSEMEM_ENABLE
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
config ARCH_SA1100
bool "SA1100-based"
select ISA
- select ARCH_DISCONTIGMEM_ENABLE
select ARCH_SPARSEMEM_ENABLE
- select ARCH_SELECT_MEMORY_MODEL
select ARCH_MTD_XIP
select GENERIC_GPIO
select GENERIC_TIME
bool "Shark"
select ISA
select ISA_DMA
+ select ZONE_DMA
select PCI
help
Support for the StrongARM based Digital DNARD machine, also known
config ARCH_LH7A40X
bool "Sharp LH7A40X"
+ select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
+ select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
help
Say Y here for systems based on one of the Sharp LH7A40X
System on a Chip processors. These CPUs include an ARM922T
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
+ select ZONE_DMA
help
Support for TI's DaVinci platform.
help
Support for TI's OMAP platform (OMAP1 and OMAP2).
- config ARCH_MSM7X00A
- bool "Qualcomm MSM7X00A"
+ config ARCH_MSM
+ bool "Qualcomm MSM"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
- Support for Qualcomm MSM7X00A based systems. This runs on the ARM11
- apps processor of the MSM7X00A and depends on a shared memory
+ Support for Qualcomm MSM7K based systems. This runs on the ARM11
+ apps processor of the MSM7K and depends on a shared memory
interface to the ARM9 modem processor which runs the baseband stack
and controls some vital subsystems (clock and power control, etc).
- <http://www.cdmatech.com/products/msm7200_chipset_solution.jsp>
endchoice
If you don't know what to do here, say N.
+ choice
+ prompt "Memory split"
+ default VMSPLIT_3G
+ help
+ Select the desired split between kernel and user memory.
+
+ If you are not absolutely sure what you are doing, leave this
+ option alone!
+
+ config VMSPLIT_3G
+ bool "3G/1G user/kernel split"
+ config VMSPLIT_2G
+ bool "2G/2G user/kernel split"
+ config VMSPLIT_1G
+ bool "1G/3G user/kernel split"
+ endchoice
+
+ config PAGE_OFFSET
+ hex
+ default 0x40000000 if VMSPLIT_1G
+ default 0x80000000 if VMSPLIT_2G
+ default 0xC0000000
+
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
default y
depends on FLATMEM
+ # Discontigmem is deprecated
config ARCH_DISCONTIGMEM_ENABLE
bool
- default (ARCH_LH7A40X && !LH7A40X_CONTIGMEM)
- help
- Say Y to support efficient handling of discontiguous physical memory,
- for architectures which are either NUMA (Non-Uniform Memory Access)
- or have huge holes in the physical address space for other reasons.
- See <file:Documentation/vm/numa> for more.
config ARCH_SPARSEMEM_ENABLE
bool
+ config ARCH_SPARSEMEM_DEFAULT
+ def_bool ARCH_SPARSEMEM_ENABLE
+
config ARCH_SELECT_MEMORY_MODEL
- bool
+ def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
config NODES_SHIFT
int
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
- ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
+ ARCH_AT91 || ARCH_DAVINCI || \
ARCH_KS8695 || MACH_RD88F5182
help
If you say Y here, the LEDs on your machine will be used
endmenu
- if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+ menu "CPU Power Management"
- menu "CPU Frequency scaling"
+ if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
source "drivers/cpufreq/Kconfig"
default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE
- endmenu
-
endif
+ source "drivers/cpuidle/Kconfig"
+
+ endmenu
+
menu "Floating point emulation"
comment "At least one emulation must be selected"
source "drivers/hwmon/Kconfig"
+ source "drivers/thermal/Kconfig"
+
source "drivers/watchdog/Kconfig"
source "drivers/ssb/Kconfig"
source "drivers/usb/Kconfig"
+ source "drivers/uwb/Kconfig"
+
source "drivers/mmc/Kconfig"
+ source "drivers/memstick/Kconfig"
+
+ source "drivers/accessibility/Kconfig"
+
source "drivers/leds/Kconfig"
source "drivers/rtc/Kconfig"
source "drivers/dca/Kconfig"
+ source "drivers/auxdisplay/Kconfig"
+
source "drivers/regulator/Kconfig"
source "drivers/uio/Kconfig"
+if ARCH_OMAP
+source "drivers/cbus/Kconfig"
+source "drivers/dsp/dspgateway/Kconfig"
+endif
+
endmenu
source "fs/Kconfig"
OBJS += head-sharpsl.o
endif
+ifeq ($(CONFIG_MACH_OMAP_PERSEUS2),y)
+OBJS += head-omap.o
+endif
+
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
ifeq ($(CONFIG_CPU_CP15),y)
OBJS += big-endian.o
endif
EXTRA_CFLAGS := -fpic -fno-builtin
- EXTRA_AFLAGS :=
+ EXTRA_AFLAGS := -Wa,-march=all
# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
# linker symbols. We only define initrd_phys and params_phys if the
unsigned int type;
};
- /* types 0-4 are defined in asm/io.h */
- #define MT_CACHECLEAN 5
- #define MT_MINICLEAN 6
- #define MT_LOW_VECTORS 7
- #define MT_HIGH_VECTORS 8
- #define MT_MEMORY 9
- #define MT_ROM 10
- #define MT_MEMORY_SO 11
-
- #define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
- #define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
+ /* types 0-3 are defined in asm/io.h */
+ #define MT_CACHECLEAN 4
+ #define MT_MINICLEAN 5
+ #define MT_LOW_VECTORS 6
+ #define MT_HIGH_VECTORS 7
+ #define MT_MEMORY 8
+ #define MT_ROM 9
++#define MT_MEMORY_SO 10
#ifdef CONFIG_MMU
extern void iotable_init(struct map_desc *, int);
#define L_PTE_PRESENT (1 << 0)
#define L_PTE_FILE (1 << 1) /* only when !PRESENT */
#define L_PTE_YOUNG (1 << 1)
- #define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */
- #define L_PTE_CACHEABLE (1 << 3) /* matches PTE */
- #define L_PTE_USER (1 << 4)
- #define L_PTE_WRITE (1 << 5)
- #define L_PTE_EXEC (1 << 6)
- #define L_PTE_DIRTY (1 << 7)
+ #define L_PTE_BUFFERABLE (1 << 2) /* obsolete, matches PTE */
+ #define L_PTE_CACHEABLE (1 << 3) /* obsolete, matches PTE */
+ #define L_PTE_DIRTY (1 << 6)
+ #define L_PTE_WRITE (1 << 7)
+ #define L_PTE_USER (1 << 8)
+ #define L_PTE_EXEC (1 << 9)
#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
+ /*
+ * These are the memory types, defined to be compatible with
+ * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
+ */
+ #define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
+ #define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
+ #define L_PTE_MT_WRITETHROUGH (0x02 << 2) /* 0010 */
+ #define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
+ #define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
+ #define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
+ #define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
+ #define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
+ #define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
+ #define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
+ #define L_PTE_MT_MASK (0x0f << 2)
+
#ifndef __ASSEMBLY__
/*
* as well as any architecture dependent bits like global/ASID and SMP
* shared mapping bits.
*/
- #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
- #define _L_PTE_READ L_PTE_USER | L_PTE_EXEC
+ #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
extern pgprot_t pgprot_user;
extern pgprot_t pgprot_kernel;
- #define PAGE_NONE pgprot_user
- #define PAGE_COPY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
- #define PAGE_SHARED __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \
- L_PTE_WRITE)
- #define PAGE_READONLY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
- #define PAGE_KERNEL pgprot_kernel
-
- #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
- #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
- #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
- #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
+ #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
+
+ #define PAGE_NONE pgprot_user
+ #define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE)
+ #define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
+ #define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER)
+ #define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
+ #define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER)
+ #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
+ #define PAGE_KERNEL pgprot_kernel
+ #define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_kernel, L_PTE_EXEC)
+
+ #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
+ #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE)
+ #define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
+ #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
+ #define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
+ #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
+ #define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
#endif /* __ASSEMBLY__ */
#define __P001 __PAGE_READONLY
#define __P010 __PAGE_COPY
#define __P011 __PAGE_COPY
- #define __P100 __PAGE_READONLY
- #define __P101 __PAGE_READONLY
- #define __P110 __PAGE_COPY
- #define __P111 __PAGE_COPY
+ #define __P100 __PAGE_READONLY_EXEC
+ #define __P101 __PAGE_READONLY_EXEC
+ #define __P110 __PAGE_COPY_EXEC
+ #define __P111 __PAGE_COPY_EXEC
#define __S000 __PAGE_NONE
#define __S001 __PAGE_READONLY
#define __S010 __PAGE_SHARED
#define __S011 __PAGE_SHARED
- #define __S100 __PAGE_READONLY
- #define __S101 __PAGE_READONLY
- #define __S110 __PAGE_SHARED
- #define __S111 __PAGE_SHARED
+ #define __S100 __PAGE_READONLY_EXEC
+ #define __S101 __PAGE_READONLY_EXEC
+ #define __S110 __PAGE_SHARED_EXEC
+ #define __S111 __PAGE_SHARED_EXEC
#ifndef __ASSEMBLY__
/*
/*
* Mark the prot value as uncacheable and unbufferable.
*/
- #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
- #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
+ #define pgprot_noncached(prot) \
+ __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_UNCACHED)
+ #define pgprot_writecombine(prot) \
+ __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_BUFFERABLE)
#define pmd_none(pmd) (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd))
#define pmd_bad(pmd) (pmd_val(pmd) & 2)
+#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE)
#define copy_pmd(pmdpd,pmdps) \
do { \
#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
- /*
- * Permanent address of a page. We never have highmem, so this is trivial.
- */
- #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
-
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
__u8 adfsdrives;
};
+/* TI OMAP specific information */
+#define ATAG_BOARD 0x414f4d50
+
+struct tag_omap {
+ u8 data[0];
+};
+
/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
#define ATAG_MEMCLK 0x41000402
*/
struct tag_acorn acorn;
+ /*
+ * OMAP specific
+ */
+ struct tag_omap omap;
+
/*
* DC21285 specific
*/
struct membank bank[NR_BANKS];
};
+ #define for_each_nodebank(iter,mi,no) \
+ for (iter = 0; iter < mi->nr_banks; iter++) \
+ if (mi->bank[iter].node == no)
+
+ #define bank_pfn_start(bank) __phys_to_pfn((bank)->start)
+ #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size)
+ #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT)
+ #define bank_phys_start(bank) (bank)->start
+ #define bank_phys_end(bank) ((bank)->start + (bank)->size)
+ #define bank_phys_size(bank) (bank)->size
+
/*
* Early command line parameters.
*/
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
+ #include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
.pins[2] = 6,
};
-static struct omap_mmc_config voiceblue_mmc_config __initdata = {
- .mmc[0] = {
- .enabled = 1,
- .power_pin = 2,
- .switch_pin = -1,
- },
-};
-
static struct omap_uart_config voiceblue_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel voiceblue_config[] = {
{ OMAP_TAG_USB, &voiceblue_usb_config },
- { OMAP_TAG_MMC, &voiceblue_mmc_config },
{ OMAP_TAG_UART, &voiceblue_uart_config },
};
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
+ #include <linux/io.h>
- #include <asm/io.h>
#include <asm/mach-types.h>
#include <mach/cpu.h>
static void omap1_uart_recalc(struct clk * clk)
{
- unsigned int val = omap_readl(clk->enable_reg);
+ unsigned int val = __raw_readl(clk->enable_reg);
if (val & clk->enable_bit)
clk->rate = 48000000;
else
{
unsigned int val;
- val = omap_readl(clk->enable_reg);
+ val = __raw_readl(clk->enable_reg);
if (rate == 12000000)
val &= ~(1 << clk->enable_bit);
else if (rate == 48000000)
val |= (1 << clk->enable_bit);
else
return -EINVAL;
- omap_writel(val, clk->enable_reg);
+ __raw_writel(val, clk->enable_reg);
clk->rate = rate;
return 0;
else
ratio_bits = (dsor - 2) << 2;
- ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
+ __raw_writew(ratio_bits, clk->enable_reg);
return 0;
}
__u16 ratio_bits;
/* Determine current rate and ensure clock is based on 96MHz APLL */
- ratio_bits = omap_readw(clk->enable_reg) & ~1;
- omap_writew(ratio_bits, clk->enable_reg);
+ ratio_bits = __raw_readw(clk->enable_reg) & ~1;
+ __raw_writew(ratio_bits, clk->enable_reg);
ratio_bits = (ratio_bits & 0xfc) >> 2;
if (ratio_bits > 6)
}
if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 |= (1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
+ regval32 = __raw_readl(clk->enable_reg);
+ regval32 |= (1 << clk->enable_bit);
+ __raw_writel(regval32, clk->enable_reg);
} else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 |= (1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
+ regval16 = __raw_readw(clk->enable_reg);
+ regval16 |= (1 << clk->enable_bit);
+ __raw_writew(regval16, clk->enable_reg);
}
return 0;
return;
if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval32 = __raw_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- __raw_writel(regval32, clk->enable_reg);
- } else {
- regval32 = omap_readl(clk->enable_reg);
- regval32 &= ~(1 << clk->enable_bit);
- omap_writel(regval32, clk->enable_reg);
- }
+ regval32 = __raw_readl(clk->enable_reg);
+ regval32 &= ~(1 << clk->enable_bit);
+ __raw_writel(regval32, clk->enable_reg);
} else {
- if (clk->flags & VIRTUAL_IO_ADDRESS) {
- regval16 = __raw_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- __raw_writew(regval16, clk->enable_reg);
- } else {
- regval16 = omap_readw(clk->enable_reg);
- regval16 &= ~(1 << clk->enable_bit);
- omap_writew(regval16, clk->enable_reg);
- }
+ regval16 = __raw_readw(clk->enable_reg);
+ regval16 &= ~(1 << clk->enable_bit);
+ __raw_writew(regval16, clk->enable_reg);
}
}
}
/* Is the clock already disabled? */
- if (clk->flags & ENABLE_REG_32BIT) {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readl(clk->enable_reg);
- else
- regval32 = omap_readl(clk->enable_reg);
- } else {
- if (clk->flags & VIRTUAL_IO_ADDRESS)
- regval32 = __raw_readw(clk->enable_reg);
- else
- regval32 = omap_readw(clk->enable_reg);
- }
+ if (clk->flags & ENABLE_REG_32BIT)
+ regval32 = __raw_readl(clk->enable_reg);
+ else
+ regval32 = __raw_readw(clk->enable_reg);
if ((regval32 & (1 << clk->enable_bit)) == 0)
return;
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+ #include <linux/io.h>
#include <mach/hardware.h>
- #include <asm/io.h>
#include <asm/mach/map.h>
#include <mach/tc.h>
#include <mach/board.h>
#include <mach/mux.h>
#include <mach/gpio.h>
+#include <mach/mmc.h>
/*-------------------------------------------------------------------------*/
static inline void omap_init_mbox(void) { }
#endif
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+ int controller_nr)
+{
+ if (controller_nr == 0) {
+ omap_cfg_reg(MMC_CMD);
+ omap_cfg_reg(MMC_CLK);
+ omap_cfg_reg(MMC_DAT0);
+ if (cpu_is_omap1710()) {
+ omap_cfg_reg(M15_1710_MMC_CLKI);
+ omap_cfg_reg(P19_1710_MMC_CMDDIR);
+ omap_cfg_reg(P20_1710_MMC_DATDIR0);
+ }
+ if (mmc_controller->slots[0].wire4) {
+ omap_cfg_reg(MMC_DAT1);
+ /* NOTE: DAT2 can be on W10 (here) or M15 */
+ if (!mmc_controller->slots[0].nomux)
+ omap_cfg_reg(MMC_DAT2);
+ omap_cfg_reg(MMC_DAT3);
+ }
+ }
+
+ /* Block 2 is on newer chips, and has many pinout options */
+ if (cpu_is_omap16xx() && controller_nr == 1) {
+ if (!mmc_controller->slots[1].nomux) {
+ omap_cfg_reg(Y8_1610_MMC2_CMD);
+ omap_cfg_reg(Y10_1610_MMC2_CLK);
+ omap_cfg_reg(R18_1610_MMC2_CLKIN);
+ omap_cfg_reg(W8_1610_MMC2_DAT0);
+ if (mmc_controller->slots[1].wire4) {
+ omap_cfg_reg(V8_1610_MMC2_DAT1);
+ omap_cfg_reg(W15_1610_MMC2_DAT2);
+ omap_cfg_reg(R10_1610_MMC2_DAT3);
+ }
+
+ /* These are needed for the level shifter */
+ omap_cfg_reg(V9_1610_MMC2_CMDDIR);
+ omap_cfg_reg(V5_1610_MMC2_DATDIR0);
+ omap_cfg_reg(W19_1610_MMC2_DATDIR1);
+ }
+
+ /* Feedback clock must be set on OMAP-1710 MMC2 */
+ if (cpu_is_omap1710())
+ omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
+ MOD_CONF_CTRL_1);
+ }
+}
+
+void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+{
+ int i;
+
+ for (i = 0; i < nr_controllers; i++) {
+ unsigned long base, size;
+ unsigned int irq = 0;
+
+ if (!mmc_data[i])
+ continue;
+
+ omap1_mmc_mux(mmc_data[i], i);
+
+ switch (i) {
+ case 0:
+ base = OMAP1_MMC1_BASE;
+ irq = INT_MMC;
+ break;
+ case 1:
+ if (!cpu_is_omap16xx())
+ return;
+ base = OMAP1_MMC2_BASE;
+ irq = INT_1610_MMC2;
+ break;
+ default:
+ continue;
+ }
+ size = OMAP1_MMC_SIZE;
+
+ omap_mmc_add(i, base, size, irq, mmc_data[i]);
+ };
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
#if defined(CONFIG_OMAP_STI)
#define OMAP1_STI_BASE 0xfffea000
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
-
- #include <asm/io.h>
+ #include <linux/io.h>
#define OMAP_DIE_ID_0 0xfffe1800
#define OMAP_DIE_ID_1 0xfffe1804
case 0x17:
system_rev |= 0x16;
break;
- case 0x24:
- system_rev |= 0x24;
- break;
default:
printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
}
#include <linux/init.h>
#include <linux/io.h>
+ #include <asm/cputype.h>
+
#include <mach/common.h>
#include <mach/control.h>
#include <mach/cpu.h>
-static u32 class;
-static void __iomem *tap_base;
-static u16 tap_prod_id;
-
-#define OMAP_TAP_IDCODE 0x0204
-#define OMAP_TAP_DIE_ID_0 0x0218
-#define OMAP_TAP_DIE_ID_1 0x021C
-#define OMAP_TAP_DIE_ID_2 0x0220
-#define OMAP_TAP_DIE_ID_3 0x0224
-
-/* system_rev fields for OMAP2 processors:
- * CPU id bits [31:16],
- * CPU device type [15:12], (unprg,normal,POP)
- * CPU revision [11:08]
- * CPU class bits [07:00]
- */
-
-struct omap_id {
- u16 hawkeye; /* Silicon type (Hawkeye id) */
- u8 dev; /* Device type from production_id reg */
- u32 type; /* combined type id copied to system_rev */
-};
-
-/* Register values to detect the OMAP version */
-static struct omap_id omap_ids[] __initdata = {
- { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
- { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
- { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
- { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
- { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
- { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
-};
-
static struct omap_chip_id omap_chip;
/**
}
EXPORT_SYMBOL(omap_chip_is);
-static u32 __init read_tap_reg(int reg)
-{
- unsigned int regval = 0;
- u32 cpuid;
-
- /* Reading the IDCODE register on 3430 ES1 results in a
- * data abort as the register is not exposed on the OCP
- * Hence reading the Cortex Rev
- */
- cpuid = read_cpuid(CPUID_ID);
-
- /* If the processor type is Cortex-A8 and the revision is 0x0
- * it means its Cortex r0p0 which is 3430 ES1
- */
- if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
-
- if (reg == tap_prod_id) {
- regval = 0x000F00F0;
- goto out;
- }
-
- switch (reg) {
- case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
- /* Making DevType as 0xF in ES1 to differ from ES2 */
- case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
- case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
- case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
- case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
- }
- } else
- regval = __raw_readl(tap_base + reg);
-
-out:
- return regval;
-
-}
-
-/*
- * _set_system_rev - set the system_rev global based on current OMAP chip type
- *
- * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
- * macros.
- */
-static void __init _set_system_rev(u32 type, u8 rev)
+int omap_type(void)
{
- u32 i, ctrl_status;
+ u32 val = 0;
- /*
- * system_rev encoding is as follows
- * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
- * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
- * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
- * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
- * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
- * system_rev & 0x000000c0 -> IDCODE revision[6:7]
- * system_rev & 0x0000003f -> sys_boot[0:5]
- */
- /* Embedding the ES revision info in type field */
- system_rev = type;
- /* Also add IDCODE revision info only two lower bits */
- system_rev |= ((rev & 0x3) << 6);
-
- /* Add in the device type and sys_boot fields (see above) */
if (cpu_is_omap24xx()) {
- i = OMAP24XX_CONTROL_STATUS;
- } else if (cpu_is_omap343x()) {
- i = OMAP343X_CONTROL_STATUS;
+ val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+ } else if (cpu_is_omap34xx()) {
+ val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else {
- printk(KERN_ERR "id: unknown CPU type\n");
- BUG();
+ pr_err("Cannot detect omap type!\n");
+ goto out;
}
- ctrl_status = omap_ctrl_readl(i);
- system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
- OMAP2_SYSBOOT_4_MASK |
- OMAP2_SYSBOOT_3_MASK |
- OMAP2_SYSBOOT_2_MASK |
- OMAP2_SYSBOOT_1_MASK |
- OMAP2_SYSBOOT_0_MASK));
- system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
-}
+ val &= OMAP2_DEVICETYPE_MASK;
+ val >>= 8;
-/*
- * _set_omap_chip - set the omap_chip global based on OMAP chip type
- *
- * Build the omap_chip bits. This variable is used by powerdomain and
- * clockdomain code to indicate whether structures are applicable for
- * the current OMAP chip type by ANDing it against a 'platform' bitfield
- * in the structure.
- */
-static void __init _set_omap_chip(void)
-{
- if (cpu_is_omap343x()) {
-
- omap_chip.oc = CHIP_IS_OMAP3430;
- if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
- omap_chip.oc |= CHIP_IS_OMAP3430ES1;
- else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
- omap_chip.oc |= CHIP_IS_OMAP3430ES2;
-
- } else if (cpu_is_omap243x()) {
+out:
+ return val;
+}
+EXPORT_SYMBOL(omap_type);
- /* Currently only supports 2430ES2.1 and 2430-all */
- omap_chip.oc |= CHIP_IS_OMAP2430;
- } else if (cpu_is_omap242x()) {
+/*----------------------------------------------------------------------------*/
- /* Currently only supports 2420ES2.1.1 and 2420-all */
- omap_chip.oc |= CHIP_IS_OMAP2420;
+#define OMAP_TAP_IDCODE 0x0204
+#define OMAP_TAP_DIE_ID_0 0x0218
+#define OMAP_TAP_DIE_ID_1 0x021C
+#define OMAP_TAP_DIE_ID_2 0x0220
+#define OMAP_TAP_DIE_ID_3 0x0224
- } else {
+#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
- /* Current CPU not supported by this code. */
- printk(KERN_WARNING "OMAP chip type code does not yet support "
- "this CPU type.\n");
- WARN_ON(1);
+struct omap_id {
+ u16 hawkeye; /* Silicon type (Hawkeye id) */
+ u8 dev; /* Device type from production_id reg */
+ u32 type; /* Combined type id copied to system_rev */
+};
- }
+/* Register values to detect the OMAP version */
+static struct omap_id omap_ids[] __initdata = {
+ { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
+ { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
+ { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
+ { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
+ { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
+ { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
+};
-}
+static void __iomem *tap_base;
+static u16 tap_prod_id;
-void __init omap2_check_revision(void)
+void __init omap24xx_check_revision(void)
{
int i, j;
- u32 idcode;
- u32 prod_id;
+ u32 idcode, prod_id;
u16 hawkeye;
- u8 dev_type;
- u8 rev;
+ u8 dev_type, rev;
idcode = read_tap_reg(OMAP_TAP_IDCODE);
prod_id = read_tap_reg(tap_prod_id);
pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
prod_id, dev_type);
- /*
- * Detection for 34xx ES2.0 and above can be done with just
- * hawkeye and rev. See TRM 1.5.2 Device Identification.
- * Note that rev cannot be used directly as ES1.0 uses value 0.
- */
- if (hawkeye == 0xb7ae) {
- system_rev = 0x34300000 | ((1 + rev) << 12);
- pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
- _set_omap_chip();
- return;
- }
-
/* Check hawkeye ids */
for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
if (hawkeye == omap_ids[i].hawkeye)
j = i;
}
- _set_system_rev(omap_ids[j].type, rev);
-
- _set_omap_chip();
-
pr_info("OMAP%04x", system_rev >> 16);
if ((system_rev >> 8) & 0x0f)
pr_info("ES%x", (system_rev >> 12) & 0xf);
pr_info("\n");
+}
+
+void __init omap34xx_check_revision(void)
+{
+ u32 cpuid, idcode;
+ u16 hawkeye;
+ u8 rev;
+ char *rev_name = "ES1.0";
+
+ /*
+ * We cannot access revision registers on ES1.0.
+ * If the processor type is Cortex-A8 and the revision is 0x0
+ * it means its Cortex r0p0 which is 3430 ES1.0.
+ */
+ cpuid = read_cpuid(CPUID_ID);
+ if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
+ system_rev = OMAP3430_REV_ES1_0;
+ goto out;
+ }
+
+ /*
+ * Detection for 34xx ES2.0 and above can be done with just
+ * hawkeye and rev. See TRM 1.5.2 Device Identification.
+ * Note that rev does not map directly to our defined processor
+ * revision numbers as ES1.0 uses value 0.
+ */
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+
+ if (hawkeye == 0xb7ae) {
+ switch (rev) {
+ case 0:
+ system_rev = OMAP3430_REV_ES2_0;
+ rev_name = "ES2.0";
+ break;
+ case 2:
+ system_rev = OMAP3430_REV_ES2_1;
+ rev_name = "ES2.1";
+ break;
+ case 3:
+ system_rev = OMAP3430_REV_ES3_0;
+ rev_name = "ES3.0";
+ break;
+ default:
+ /* Use the latest known revision as default */
+ system_rev = OMAP3430_REV_ES3_0;
+ rev_name = "Unknown revision\n";
+ }
+ }
+
+out:
+ pr_info("OMAP%04x %s\n", system_rev >> 16, rev_name);
+}
+
+/*
+ * Try to detect the exact revision of the omap we're running on
+ */
+void __init omap2_check_revision(void)
+{
+ /*
+ * At this point we have an idea about the processor revision set
+ * earlier with omap2_set_globals_tap().
+ */
+ if (cpu_is_omap24xx())
+ omap24xx_check_revision();
+ else if (cpu_is_omap34xx())
+ omap34xx_check_revision();
+ else
+ pr_err("OMAP revision unknown, please fix!\n");
+ /*
+ * OK, now we know the exact revision. Initialize omap_chip bits
+ * for powerdowmain and clockdomain code.
+ */
+ if (cpu_is_omap243x()) {
+ /* Currently only supports 2430ES2.1 and 2430-all */
+ omap_chip.oc |= CHIP_IS_OMAP2430;
+ } else if (cpu_is_omap242x()) {
+ /* Currently only supports 2420ES2.1.1 and 2420-all */
+ omap_chip.oc |= CHIP_IS_OMAP2420;
+ } else if (cpu_is_omap343x()) {
+ omap_chip.oc = CHIP_IS_OMAP3430;
+ if (system_rev == OMAP3430_REV_ES1_0)
+ omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+ else if (system_rev > OMAP3430_REV_ES1_0)
+ omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+ } else {
+ pr_err("Uninitialized omap_chip, please fix!\n");
+ }
}
+/*
+ * Set up things for map_io and processor detection later on. Gets called
+ * pretty much first thing from board init. For multi-omap, this gets
+ * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
+ * detect the exact revision later on in omap2_detect_revision() once map_io
+ * is done.
+ */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
- class = omap2_globals->class;
+ system_rev = omap2_globals->class;
tap_base = omap2_globals->tap;
- if (class == 0x3430)
+ if (cpu_is_omap34xx())
tap_prod_id = 0x0210;
else
tap_prod_id = 0x0208;
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
+ #include <linux/io.h>
#include <mach/mailbox.h>
#include <mach/irqs.h>
- #include <asm/io.h>
#define MAILBOX_REVISION 0x00
#define MAILBOX_SYSCONFIG 0x10
static inline unsigned int mbox_read_reg(unsigned int reg)
{
- return __raw_readl(mbox_base + reg);
+ return __raw_readl((void __iomem *)(mbox_base + reg));
}
static inline void mbox_write_reg(unsigned int val, unsigned int reg)
{
- __raw_writel(val, mbox_base + reg);
+ __raw_writel(val, (void __iomem *)(mbox_base + reg));
}
/* Mailbox H/W preparations */
#include <linux/mman.h>
#include <linux/nodemask.h>
+ #include <asm/cputype.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/sizes.h>
DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
- extern void _stext, _etext, __data_start, _end;
- extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
/*
* empty_zero_page is a special page that is used for
* zero-initialized data and COW.
.policy = "uncached",
.cr_mask = CR_W|CR_C,
.pmd = PMD_SECT_UNCACHED,
- .pte = 0,
+ .pte = L_PTE_MT_UNCACHED,
}, {
.policy = "buffered",
.cr_mask = CR_C,
.pmd = PMD_SECT_BUFFERED,
- .pte = PTE_BUFFERABLE,
+ .pte = L_PTE_MT_BUFFERABLE,
}, {
.policy = "writethrough",
.cr_mask = 0,
.pmd = PMD_SECT_WT,
- .pte = PTE_CACHEABLE,
+ .pte = L_PTE_MT_WRITETHROUGH,
}, {
.policy = "writeback",
.cr_mask = 0,
.pmd = PMD_SECT_WB,
- .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
+ .pte = L_PTE_MT_WRITEBACK,
}, {
.policy = "writealloc",
.cr_mask = 0,
.pmd = PMD_SECT_WBWA,
- .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
+ .pte = L_PTE_MT_WRITEALLOC,
}
};
static struct mem_type mem_types[] = {
[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
- .prot_pte = PROT_PTE_DEVICE,
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
+ L_PTE_SHARED,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
.domain = DOMAIN_IO,
},
[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
- .prot_pte = PROT_PTE_DEVICE,
- .prot_pte_ext = PTE_EXT_TEX(2),
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
.domain = DOMAIN_IO,
},
[MT_DEVICE_CACHED] = { /* ioremap_cached */
- .prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
.domain = DOMAIN_IO,
},
- [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
- .prot_pte = PROT_PTE_DEVICE,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
- PMD_SECT_TEX(1),
- .domain = DOMAIN_IO,
- },
[MT_DEVICE_WC] = { /* ioremap_wc */
- .prot_pte = PROT_PTE_DEVICE,
+ .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
.prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PROT_SECT_DEVICE,
+ .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE,
.domain = DOMAIN_IO,
},
[MT_CACHECLEAN] = {
[MT_ROM] = {
.prot_sect = PMD_TYPE_SECT,
.domain = DOMAIN_KERNEL,
+ },
+ [MT_MEMORY_SO] = {
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_UNCACHED,
+ .domain = DOMAIN_KERNEL,
},
};
{
struct cachepolicy *cp;
unsigned int cr = get_cr();
- unsigned int user_pgprot, kern_pgprot;
+ unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
int cpu_arch = cpu_architecture();
int i;
cachepolicy = CPOLICY_WRITEBACK;
ecc_mask = 0;
}
+ #ifdef CONFIG_SMP
+ cachepolicy = CPOLICY_WRITEALLOC;
+ #endif
/*
* On non-Xscale3 ARMv5-and-older systems, use CB=01
* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
*/
if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
- mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
- } else {
- mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_BUFFERABLE;
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
+ mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
}
/*
}
cp = &cache_policies[cachepolicy];
- kern_pgprot = user_pgprot = cp->pte;
+ vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+
+ #ifndef CONFIG_SMP
+ /*
+ * Only use write-through for non-SMP systems
+ */
+ if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+ vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
+ #endif
/*
* Enable CPU-specific coherency if supported.
/*
* Mark the device area as "shared device"
*/
- mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
#ifdef CONFIG_SMP
*/
user_pgprot |= L_PTE_SHARED;
kern_pgprot |= L_PTE_SHARED;
+ vecs_pgprot |= L_PTE_SHARED;
mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
#endif
}
for (i = 0; i < 16; i++) {
unsigned long v = pgprot_val(protection_map[i]);
- v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
- protection_map[i] = __pgprot(v);
+ protection_map[i] = __pgprot(v | user_pgprot);
}
- mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
- mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
+ mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
+ mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
- if (cpu_arch >= CPU_ARCH_ARMv5) {
- #ifndef CONFIG_SMP
- /*
- * Only use write-through for non-SMP systems
- */
- mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
- mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
- #endif
- } else {
+ if (cpu_arch < CPU_ARCH_ARMv5)
mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
- }
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
pte = pte_offset_kernel(pmd, addr);
do {
- set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
- type->prot_pte_ext);
+ set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
pfn++;
} while (pte++, addr += PAGE_SIZE, addr != end);
}
create_mapping(io_desc + i);
}
+ static unsigned long __initdata vmalloc_reserve = SZ_128M;
+
+ /*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the vmalloc
+ * area - the default is 128m.
+ */
+ static void __init early_vmalloc(char **arg)
+ {
+ vmalloc_reserve = memparse(*arg, arg);
+
+ if (vmalloc_reserve < SZ_16M) {
+ vmalloc_reserve = SZ_16M;
+ printk(KERN_WARNING
+ "vmalloc area too small, limiting to %luMB\n",
+ vmalloc_reserve >> 20);
+ }
+ }
+ __early_param("vmalloc=", early_vmalloc);
+
+ #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
+
static int __init check_membank_valid(struct membank *mb)
{
/*
- * Check whether this memory region has non-zero size.
+ * Check whether this memory region has non-zero size or
+ * invalid node number.
*/
- if (mb->size == 0)
+ if (mb->size == 0 || mb->node >= MAX_NUMNODES)
return 0;
/*
static void __init sanity_check_meminfo(struct meminfo *mi)
{
- int i;
- int j;
+ int i, j;
for (i = 0, j = 0; i < mi->nr_banks; i++) {
if (check_membank_valid(&mi->bank[i]))
#include <linux/platform_device.h>
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
-
- #include <asm/io.h>
+ #include <linux/io.h>
#include <mach/clock.h>
unsigned long flags;
list_for_each_entry(ck, &clocks, node) {
- if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
- ck->enable_reg == 0)
+ if (ck->usecount > 0 ||
+ (ck->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)))
+ continue;
+
+ if (cpu_class_is_omap1() && ck->enable_reg == 0)
continue;
spin_lock_irqsave(&clockfw_lock, flags);
if (c->id != 0)
sprintf(p, ":%d", c->id);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
- if (IS_ERR(d))
- return PTR_ERR(d);
+ if (!d)
+ return -ENOMEM;
c->dent = d;
d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
- if (IS_ERR(d)) {
- err = PTR_ERR(d);
+ if (!d) {
+ err = -ENOMEM;
goto err_out;
}
d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
- if (IS_ERR(d)) {
- err = PTR_ERR(d);
+ if (!d) {
+ err = -ENOMEM;
goto err_out;
}
d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
- if (IS_ERR(d)) {
- err = PTR_ERR(d);
+ if (!d) {
+ err = -ENOMEM;
goto err_out;
}
return 0;
int err;
d = debugfs_create_dir("clock", NULL);
- if (IS_ERR(d))
- return PTR_ERR(d);
+ if (!d)
+ return -ENOMEM;
clk_debugfs_root = d;
list_for_each_entry(c, &clocks, node) {
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
+ #include <linux/io.h>
#include <mach/hardware.h>
- #include <asm/io.h>
#include <asm/system.h>
+#include <mach/clock.h>
#define VERY_HI_RATE 900000000
+static struct cpufreq_frequency_table *freq_table;
+
#ifdef CONFIG_ARCH_OMAP1
#define MPU_CLK "mpu"
#else
int omap_verify_speed(struct cpufreq_policy *policy)
{
+ if (freq_table)
+ return cpufreq_frequency_table_verify(policy, freq_table);
+
if (policy->cpu)
return -EINVAL;
struct cpufreq_freqs freqs;
int ret = 0;
+ /* Ensure desired rate is within allowed range. Some govenors
+ * (ondemand) will just pass target_freq=0 to get the minimum. */
+ if (target_freq < policy->cpuinfo.min_freq)
+ target_freq = policy->cpuinfo.min_freq;
+ if (target_freq > policy->cpuinfo.max_freq)
+ target_freq = policy->cpuinfo.max_freq;
+
freqs.old = omap_getspeed(0);
freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
freqs.cpu = 0;
+ if (freqs.old == freqs.new)
+ return ret;
+
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- ret = clk_set_rate(mpu_clk, target_freq * 1000);
+#ifdef CONFIG_CPU_FREQ_DEBUG
+ printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n",
+ freqs.old, freqs.new);
+#endif
+ ret = clk_set_rate(mpu_clk, freqs.new * 1000);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
return ret;
static int __init omap_cpu_init(struct cpufreq_policy *policy)
{
+ int result = 0;
+
mpu_clk = clk_get(NULL, MPU_CLK);
if (IS_ERR(mpu_clk))
return PTR_ERR(mpu_clk);
if (policy->cpu != 0)
return -EINVAL;
+
policy->cur = policy->min = policy->max = omap_getspeed(0);
- policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
- policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000;
- policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+
+ clk_init_cpufreq_table(&freq_table);
+ if (freq_table) {
+ result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ if (!result)
+ cpufreq_frequency_table_get_attr(freq_table,
+ policy->cpu);
+ } else {
+ policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
+ policy->cpuinfo.max_freq = clk_round_rate(mpu_clk,
+ VERY_HI_RATE) / 1000;
+ }
+
+ /* FIXME: what's the actual transition time? */
+ policy->cpuinfo.transition_latency = 10 * 1000 * 1000;
return 0;
}
return 0;
}
+static struct freq_attr *omap_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
static struct cpufreq_driver omap_driver = {
.flags = CPUFREQ_STICKY,
.verify = omap_verify_speed,
.init = omap_cpu_init,
.exit = omap_cpu_exit,
.name = "omap",
+ .attr = omap_cpufreq_attr,
};
static int __init omap_cpufreq_init(void)
}
arch_initcall(omap_cpufreq_init);
+
+/*
+ * if ever we want to remove this, upon cleanup call:
+ *
+ * cpufreq_unregister_driver()
+ * cpufreq_frequency_table_put_attr()
+ */
+
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/delay.h>
+ #include <linux/io.h>
#include <mach/hardware.h>
#include <mach/dmtimer.h>
- #include <asm/io.h>
#include <mach/irqs.h>
/* register offsets */
{ .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
- { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
+ { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
};
static const char *omap3_dm_source_names[] __initdata = {
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/bootmem.h>
+ #include <linux/io.h>
#include <mach/hardware.h>
- #include <asm/io.h>
#include <asm/mach/map.h>
#include <mach/board.h>
config_invalid = 1;
return;
}
- if (rg.paddr)
+ if (rg.paddr) {
reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT);
- reserved += rg.size;
+ reserved += rg.size;
+ }
omapfb_config.mem_desc.region[i] = rg;
configured_regions++;
}
u32 level_mask;
spinlock_t lock;
struct gpio_chip chip;
+ struct clk *dbck;
};
#define METHOD_MPUIO 0
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
val = __raw_readl(reg);
- if (enable)
+ if (enable && !(val & l))
val |= l;
- else
+ else if (!enable && val & l)
val &= ~l;
+ else
+ return;
+
+ if (cpu_is_omap34xx())
+ enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
__raw_writel(val, reg);
}
gpio_irq = bank->virtual_irq_start;
for (; isr != 0; isr >>= 1, gpio_irq++) {
- struct irq_desc *d;
-
if (!(isr & 1))
continue;
- d = irq_desc + gpio_irq;
- desc_handle_irq(gpio_irq, d);
+ generic_handle_irq(gpio_irq);
}
}
/* if bank has any level sensitive GPIO pin interrupt
spin_unlock_irqrestore(&bank->lock, flags);
}
+static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct gpio_bank *bank;
+
+ bank = container_of(chip, struct gpio_bank, chip);
+ return bank->virtual_irq_start + offset;
+}
+
/*---------------------------------------------------------------------*/
static int initialized;
#endif
#if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
#endif
int i;
int gpio = 0;
struct gpio_bank *bank;
-#if defined(CONFIG_ARCH_OMAP3)
char clk_name[11];
-#endif
initialized = 1;
printk(KERN_ERR "Could not get %s\n", clk_name);
else
clk_enable(gpio_iclks[i]);
- sprintf(clk_name, "gpio%d_fck", i + 1);
- gpio_fclks[i] = clk_get(NULL, clk_name);
- if (IS_ERR(gpio_fclks[i]))
- printk(KERN_ERR "Could not get %s\n", clk_name);
- else
- clk_enable(gpio_fclks[i]);
}
}
#endif
bank->chip.get = gpio_get;
bank->chip.direction_output = gpio_output;
bank->chip.set = gpio_set;
+ bank->chip.to_irq = gpio_2irq;
if (bank_is_mpuio(bank)) {
bank->chip.label = "mpuio";
#ifdef CONFIG_ARCH_OMAP16XX
}
set_irq_chained_handler(bank->irq, gpio_irq_handler);
set_irq_data(bank->irq, bank);
+
+ if (cpu_is_omap34xx()) {
+ sprintf(clk_name, "gpio%d_dbck", i + 1);
+ bank->dbck = clk_get(NULL, clk_name);
+ if (IS_ERR(bank->dbck))
+ printk(KERN_ERR "Could not get %s\n", clk_name);
+ }
}
/* Enable system clock for GPIO module.
obj-$(CONFIG_FB_I810) += video/i810/
obj-$(CONFIG_FB_INTEL) += video/intelfb/
+# we also need input/serio early so serio bus is initialized by the time
+# serial drivers start registering their serio ports
+obj-$(CONFIG_SERIO) += input/serio/
obj-y += serial/
obj-$(CONFIG_PARPORT) += parport/
-obj-y += base/ block/ misc/ mfd/ net/ media/
+obj-y += base/ block/ misc/ mfd/ net/ media/ cbus/
+obj-y += i2c/
+obj-y += cbus/
+obj-$(CONFIG_ARCH_OMAP) += dsp/dspgateway/
obj-$(CONFIG_NUBUS) += nubus/
obj-$(CONFIG_ATM) += atm/
obj-y += macintosh/
obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/
obj-$(CONFIG_PCI) += usb/
obj-$(CONFIG_USB_GADGET) += usb/gadget/
-obj-$(CONFIG_SERIO) += input/serio/
obj-$(CONFIG_GAMEPORT) += input/gameport/
obj-$(CONFIG_INPUT) += input/
obj-$(CONFIG_I2O) += message/
obj-$(CONFIG_RTC_LIB) += rtc/
-obj-y += i2c/
obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_POWER_SUPPLY) += power/
obj-$(CONFIG_HWMON) += hwmon/
obj-y += lguest/
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_CPU_IDLE) += cpuidle/
+ obj-y += idle/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_MEMSTICK) += memstick/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_SSB) += ssb/
obj-$(CONFIG_VIRTIO) += virtio/
obj-$(CONFIG_REGULATOR) += regulator/
+ obj-$(CONFIG_STAGING) += staging/
+ obj-$(CONFIG_UWB) += uwb/
depends on I2C
help
If you say yes here you get support for National Semiconductor LM90,
- LM86, LM89 and LM99, Analog Devices ADM1032 and Maxim MAX6657,
- MAX6658, MAX6659, MAX6680 and MAX6681 sensor chips.
-
- The Analog Devices ADT7461 sensor chip is also supported, but only
- if found in ADM1032 compatibility mode.
+ LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, and Maxim
+ MAX6646, MAX6647, MAX6649, MAX6657, MAX6658, MAX6659, MAX6680 and
+ MAX6681 sensor chips.
This driver can also be built as a module. If so, the module
will be called lm90.
This driver can also be built as a module. If so, the module
will be called lm93.
+ config SENSORS_MAX1111
+ tristate "Maxim MAX1111 Multichannel, Serial 8-bit ADC chip"
+ depends on SPI_MASTER
+ help
+ Say y here to support Maxim's MAX1111 ADC chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called max1111.
+
config SENSORS_MAX1619
tristate "Maxim MAX1619 sensor chip"
depends on I2C
This driver can also be built as a module. If so, the module
will be called w83627ehf.
+ config SENSORS_ULTRA45
+ tristate "Sun Ultra45 PIC16F747"
+ depends on SPARC64
+ help
+ This driver provides support for the Ultra45 workstation environmental
+ sensors.
+
config SENSORS_HDAPS
tristate "IBM Hard Drive Active Protection System (hdaps)"
depends on INPUT && X86
Say Y here if you have an applicable laptop and want to experience
the awesome power of applesmc.
+config SENSORS_TSC210X
+ tristate "TI TSC210x battery & temperature sensors"
+ depends on HWMON && SPI_MASTER
+ select SPI_TSC210X
+ help
+ Say Y if your board has a TSC210x chip and you want to
+ have its battery state, auxiliary input and/or temperature
+ sensors exported through hwmon.
+
+ This driver can also be built as a module. In this case
+ the module will be called tsc210x_sensors.
+
+config SENSORS_OMAP34XX
+ tristate "TI OMAP34xx internal temperature sensor"
+ depends on ARCH_OMAP3 && HIGH_RES_TIMERS
+
config HWMON_DEBUG_CHIP
bool "Hardware Monitoring Chip debugging messages"
default n
obj-$(CONFIG_SENSORS_FSCPOS) += fscpos.o
obj-$(CONFIG_SENSORS_GL518SM) += gl518sm.o
obj-$(CONFIG_SENSORS_GL520SM) += gl520sm.o
+ obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
obj-$(CONFIG_SENSORS_HDAPS) += hdaps.o
obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o
obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o
obj-$(CONFIG_SENSORS_LM90) += lm90.o
obj-$(CONFIG_SENSORS_LM92) += lm92.o
obj-$(CONFIG_SENSORS_LM93) += lm93.o
+ obj-$(CONFIG_SENSORS_MAX1111) += max1111.o
obj-$(CONFIG_SENSORS_MAX1619) += max1619.o
obj-$(CONFIG_SENSORS_MAX6650) += max6650.o
obj-$(CONFIG_SENSORS_PC87360) += pc87360.o
obj-$(CONFIG_SENSORS_VT8231) += vt8231.o
obj-$(CONFIG_SENSORS_W83627EHF) += w83627ehf.o
obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o
+obj-$(CONFIG_SENSORS_TSC210X) += tsc210x_sensors.o
obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
+obj-$(CONFIG_SENSORS_OMAP34XX) += omap34xx_temp.o
ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y)
EXTRA_CFLAGS += -DDEBUG
config I2C_AMD756_S4882
tristate "SMBus multiplexing on the Tyan S4882"
- depends on I2C_AMD756 && EXPERIMENTAL
+ depends on I2C_AMD756 && X86 && EXPERIMENTAL
help
Enabling this option will add specific SMBus support for the Tyan
S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
ICH9
Tolapai
ICH10
+ PCH
This driver can also be built as a module. If so, the module
will be called i2c-i801.
config I2C_NFORCE2_S4985
tristate "SMBus multiplexing on the Tyan S4985"
- depends on I2C_NFORCE2 && EXPERIMENTAL
+ depends on I2C_NFORCE2 && X86 && EXPERIMENTAL
help
Enabling this option will add specific SMBus support for the Tyan
S4985 motherboard. On this 4-CPU board, the SMBus is multiplexed
will be called i2c-via.
config I2C_VIAPRO
- tristate "VIA VT82C596/82C686/82xx and CX700"
+ tristate "VIA VT82C596/82C686/82xx and CX700/VX800/VX820"
depends on PCI
help
If you say yes to this option, support will be included for the VIA
VT8237R/A/S
VT8251
CX700
+ VX800
+ VX820
This driver can also be built as a module. If so, the module
will be called i2c-viapro.
This is a very simple bitbanging I2C driver utilizing the
arch-neutral GPIO API to control the SCL and SDA lines.
+ config I2C_HIGHLANDER
+ tristate "Highlander FPGA SMBus interface"
+ depends on SH_HIGHLANDER
+ help
+ If you say yes to this option, support will be included for
+ the SMBus interface located in the FPGA on various Highlander
+ boards, particularly the R0P7780LC0011RL and R0P7785LC0011RL
+ FPGAs. This is wholly unrelated to the SoC I2C.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-highlander.
+
config I2C_IBM_IIC
tristate "IBM PPC 4xx on-chip I2C interface"
depends on 4xx
default y if MACH_OMAP_H3 || MACH_OMAP_OSK
help
If you say yes to this option, support will be included for the
- I2C interface on the Texas Instruments OMAP1/2 family of processors.
- Like OMAP1510/1610/1710/5912 and OMAP242x.
+ I2C interface on the Texas Instruments OMAP1/2/3 family of
+ processors.
+ Like OMAP1510/1610/1710/5912, OMAP242x, OMAP34x and OMAP35x.
For details see http://www.ti.com/omap.
+config I2C2_OMAP_BEAGLE
+ bool "Enable I2C2 for OMAP3 BeagleBoard"
+ depends on ARCH_OMAP && MACH_OMAP3_BEAGLE
+ select OMAP_MUX
+ default n
+ help
+ Say Y here if you want to enable I2C bus 2 at OMAP3 based
+ BeagleBoard.
+ I2C2 at BeagleBoard is connected to expansion connector, i.e. unused
+ if nothing is connected to this connector. As internal OMAP3 pull up
+ resistors are not strong enough, enabled but unused I2C2 bus results
+ in error messages (e.g. I2C timeouts). Enable this only if you have
+ something connected to I2C2 at board's expansion connector and this
+ extension has additional pull up resistors for I2C2 bus.
+
config I2C_PASEMI
tristate "PA Semi SMBus interface"
depends on PPC_PASEMI && PCI
obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
+ obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
obj-$(CONFIG_I2C_STUB) += i2c-stub.o
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
+obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
EXTRA_CFLAGS += -DDEBUG
#
# Miscellaneous I2C chip drivers configuration
#
+ # *** DEPRECATED! Do not add new entries! See Makefile ***
+ #
menu "Miscellaneous I2C Chip support"
This driver can also be built as a module. If so, the module
will be called tps65010.
+config SENSORS_TLV320AIC23
+ tristate "Texas Instruments TLV320AIC23 Codec"
+ depends on I2C && I2C_OMAP
+ help
+ If you say yes here you get support for the I2C control
+ interface for Texas Instruments TLV320AIC23 audio codec.
+
+config GPIOEXPANDER_OMAP
+ bool "GPIO Expander PCF8574PWR for OMAP"
+ depends on I2C && (ARCH_OMAP16XX || ARCH_OMAP24XX)
+ help
+ If you say yes here you get support for I/O expander calls
+ to configure IrDA, Camera and audio devices.
+
+config TWL4030_MADC
+ tristate "TWL4030 MADC Driver"
+ depends on TWL4030_CORE
+ help
+ The TWL4030 Monitoring ADC driver enables the host
+ processor to monitor analog signals using analog-to-digital
+ conversions on the input source. TWL4030 MADC provides the
+ following features:
+ - Single 10-bit ADC with successive approximation register (SAR) conversion;
+ - Analog multiplexer for 16 inputs;
+ - Seven (of the 16) inputs are freely available;
+ - Battery voltage monitoring;
+ - Concurrent conversion request management;
+ - Interrupt signal to Primary Interrupt Handler;
+ - Averaging feature;
+ - Selective enable/disable of the averaging feature.
+
+ Say 'y' here to statically link this module into the kernel or 'm'
+ to build it as a dinamically loadable module. The module will be
+ called twl4030-madc.ko
+
+config TWL4030_USB
+ tristate "TWL4030 USB Transceiver Driver"
+ depends on TWL4030_CORE
+
+config TWL4030_PWRBUTTON
+ tristate "TWL4030 Power button Driver"
+ depends on TWL4030_CORE
+
+config TWL4030_POWEROFF
+ tristate "TWL4030 device poweroff"
+ depends on TWL4030_CORE
+
config SENSORS_MAX6875
tristate "Maxim MAX6875 Power supply supervisor"
depends on EXPERIMENTAL
This driver can also be built as a module. If so, the module
will be called tsl2550.
+config SENSORS_TSL2563
+ tristate "Taos TSL2563 ambient light sensor"
+ depends on I2C && HWMON
+ help
+ If you say yes here you get support for the Taos TSL2563
+ ambient light sensor.
+
+ This driver can also be built as a module. If so, the module
+ will be called tsl2563.
+
+config LP5521
+ tristate "LP5521 LED driver chip"
+ depends on I2C
+ help
+ If you say yes here you get support for the National Semiconductor
+ LP5521 LED driver.
+
config MENELAUS
bool "TWL92330/Menelaus PM chip"
depends on I2C=y && ARCH_OMAP24XX
and other features that are often used in portable devices like
cell phones and PDAs.
+ config MCU_MPC8349EMITX
+ tristate "MPC8349E-mITX MCU driver"
+ depends on I2C && PPC_83xx
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ help
+ Say Y here to enable soft power-off functionality on the Freescale
+ boards with the MPC8349E-mITX-compatible MCU chips. This driver will
+ also register MCU GPIOs with the generic GPIO API, so you'll able
+ to use MCU pins as GPIOs.
+
endmenu
#
# Makefile for miscellaneous I2C chip drivers.
#
- # Think twice before you add a new driver to this directory.
+ # Do not add new drivers to this directory! It is DEPRECATED.
+ #
# Device drivers are better grouped according to the functionality they
# implement rather than to the bus they are connected to. In particular:
# * Hardware monitoring chip drivers go to drivers/hwmon
obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o
obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o
obj-$(CONFIG_TPS65010) += tps65010.o
+obj-$(CONFIG_SENSORS_TLV320AIC23) += tlv320aic23.o
+obj-$(CONFIG_GPIOEXPANDER_OMAP) += gpio_expander_omap.o
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o
- obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
+ obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
+obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
+obj-$(CONFIG_TWL4030_POWEROFF) += twl4030-poweroff.o
+obj-$(CONFIG_TWL4030_PWRBUTTON) += twl4030-pwrbutton.o
+obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o
+obj-$(CONFIG_RTC_X1205_I2C) += x1205.o
+obj-$(CONFIG_LP5521) += lp5521.o
ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
EXTRA_CFLAGS += -DDEBUG
endif
-
+
/*
* Copyright (C) 2004 Texas Instruments, Inc.
*
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
+#include <linux/i2c/menelaus.h>
+#include <asm/mach-types.h>
#include <asm/mach/irq.h>
#include <mach/gpio.h>
-#include <mach/menelaus.h>
#define DRIVER_NAME "menelaus"
-#define MENELAUS_I2C_ADDRESS 0x72
-
-#define MENELAUS_REV 0x01
-#define MENELAUS_VCORE_CTRL1 0x02
-#define MENELAUS_VCORE_CTRL2 0x03
-#define MENELAUS_VCORE_CTRL3 0x04
-#define MENELAUS_VCORE_CTRL4 0x05
-#define MENELAUS_VCORE_CTRL5 0x06
-#define MENELAUS_DCDC_CTRL1 0x07
-#define MENELAUS_DCDC_CTRL2 0x08
-#define MENELAUS_DCDC_CTRL3 0x09
-#define MENELAUS_LDO_CTRL1 0x0A
-#define MENELAUS_LDO_CTRL2 0x0B
-#define MENELAUS_LDO_CTRL3 0x0C
-#define MENELAUS_LDO_CTRL4 0x0D
-#define MENELAUS_LDO_CTRL5 0x0E
-#define MENELAUS_LDO_CTRL6 0x0F
-#define MENELAUS_LDO_CTRL7 0x10
-#define MENELAUS_LDO_CTRL8 0x11
-#define MENELAUS_SLEEP_CTRL1 0x12
-#define MENELAUS_SLEEP_CTRL2 0x13
-#define MENELAUS_DEVICE_OFF 0x14
-#define MENELAUS_OSC_CTRL 0x15
-#define MENELAUS_DETECT_CTRL 0x16
-#define MENELAUS_INT_MASK1 0x17
-#define MENELAUS_INT_MASK2 0x18
-#define MENELAUS_INT_STATUS1 0x19
-#define MENELAUS_INT_STATUS2 0x1A
-#define MENELAUS_INT_ACK1 0x1B
-#define MENELAUS_INT_ACK2 0x1C
-#define MENELAUS_GPIO_CTRL 0x1D
-#define MENELAUS_GPIO_IN 0x1E
-#define MENELAUS_GPIO_OUT 0x1F
-#define MENELAUS_BBSMS 0x20
-#define MENELAUS_RTC_CTRL 0x21
-#define MENELAUS_RTC_UPDATE 0x22
-#define MENELAUS_RTC_SEC 0x23
-#define MENELAUS_RTC_MIN 0x24
-#define MENELAUS_RTC_HR 0x25
-#define MENELAUS_RTC_DAY 0x26
-#define MENELAUS_RTC_MON 0x27
-#define MENELAUS_RTC_YR 0x28
-#define MENELAUS_RTC_WKDAY 0x29
-#define MENELAUS_RTC_AL_SEC 0x2A
-#define MENELAUS_RTC_AL_MIN 0x2B
-#define MENELAUS_RTC_AL_HR 0x2C
-#define MENELAUS_RTC_AL_DAY 0x2D
-#define MENELAUS_RTC_AL_MON 0x2E
-#define MENELAUS_RTC_AL_YR 0x2F
-#define MENELAUS_RTC_COMP_MSB 0x30
-#define MENELAUS_RTC_COMP_LSB 0x31
-#define MENELAUS_S1_PULL_EN 0x32
-#define MENELAUS_S1_PULL_DIR 0x33
-#define MENELAUS_S2_PULL_EN 0x34
-#define MENELAUS_S2_PULL_DIR 0x35
-#define MENELAUS_MCT_CTRL1 0x36
-#define MENELAUS_MCT_CTRL2 0x37
-#define MENELAUS_MCT_CTRL3 0x38
-#define MENELAUS_MCT_PIN_ST 0x39
-#define MENELAUS_DEBOUNCE1 0x3A
-
-#define IH_MENELAUS_IRQS 12
-#define MENELAUS_MMC_S1CD_IRQ 0 /* MMC slot 1 card change */
-#define MENELAUS_MMC_S2CD_IRQ 1 /* MMC slot 2 card change */
-#define MENELAUS_MMC_S1D1_IRQ 2 /* MMC DAT1 low in slot 1 */
-#define MENELAUS_MMC_S2D1_IRQ 3 /* MMC DAT1 low in slot 2 */
-#define MENELAUS_LOWBAT_IRQ 4 /* Low battery */
-#define MENELAUS_HOTDIE_IRQ 5 /* Hot die detect */
-#define MENELAUS_UVLO_IRQ 6 /* UVLO detect */
-#define MENELAUS_TSHUT_IRQ 7 /* Thermal shutdown */
-#define MENELAUS_RTCTMR_IRQ 8 /* RTC timer */
-#define MENELAUS_RTCALM_IRQ 9 /* RTC alarm */
-#define MENELAUS_RTCERR_IRQ 10 /* RTC error */
-#define MENELAUS_PSHBTN_IRQ 11 /* Push button */
-#define MENELAUS_RESERVED12_IRQ 12 /* Reserved */
-#define MENELAUS_RESERVED13_IRQ 13 /* Reserved */
-#define MENELAUS_RESERVED14_IRQ 14 /* Reserved */
-#define MENELAUS_RESERVED15_IRQ 15 /* Reserved */
static void menelaus_work(struct work_struct *_menelaus);
int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value);
if (val < 0) {
- pr_err(DRIVER_NAME ": write error");
+ dev_err(&the_menelaus->client->dev, "write error");
return val;
}
int val = i2c_smbus_read_byte_data(the_menelaus->client, reg);
if (val < 0)
- pr_err(DRIVER_NAME ": read error");
+ dev_err(&the_menelaus->client->dev, "read error");
return val;
}
return;
if (!(reg & 0x1))
- card_mask |= (1 << 0);
+ card_mask |= MCT_PIN_ST_S1_CD_ST;
if (!(reg & 0x2))
- card_mask |= (1 << 1);
+ card_mask |= MCT_PIN_ST_S2_CD_ST;
if (menelaus_hw->mmc_callback)
menelaus_hw->mmc_callback(menelaus_hw->mmc_callback_data,
val = ret;
if (slot == 1) {
if (enable)
- val |= 1 << 2;
+ val |= MCT_CTRL1_S1_CMD_OD;
else
- val &= ~(1 << 2);
+ val &= ~MCT_CTRL1_S1_CMD_OD;
} else {
if (enable)
- val |= 1 << 3;
+ val |= MCT_CTRL1_S2_CMD_OD;
else
- val &= ~(1 << 3);
+ val &= ~MCT_CTRL1_S2_CMD_OD;
}
ret = menelaus_write_reg(MENELAUS_MCT_CTRL1, val);
mutex_unlock(&the_menelaus->lock);
ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
if (ret < 0)
goto out;
- ret |= 0x02;
+ ret |= GPIO2_DIR_INPUT;
if (enable)
- ret |= 1 << 5;
+ ret |= GPIO_CTRL_SLOTSELEN;
else
- ret &= ~(1 << 5);
+ ret &= ~GPIO_CTRL_SLOTSELEN;
ret = menelaus_write_reg(MENELAUS_GPIO_CTRL, ret);
out:
mutex_unlock(&the_menelaus->lock);
}
EXPORT_SYMBOL(menelaus_set_slot_sel);
+int menelaus_enable_slot(int slot, int enable)
+{
+ int ret, val;
+
+ mutex_lock(&the_menelaus->lock);
+ ret = menelaus_read_reg(MENELAUS_MCT_CTRL3);
+ if (ret < 0)
+ goto out;
+ val = ret;
+ if (slot == 1) {
+ if (enable)
+ val |= MCT_CTRL3_SLOT1_EN;
+ else
+ val &= ~MCT_CTRL3_SLOT1_EN;
+ } else {
+ if (enable)
+ val |= MCT_CTRL3_SLOT2_EN;
+ else
+ val &= MCT_CTRL3_SLOT2_EN;
+ }
+ ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val);
+
+out:
+ mutex_unlock(&the_menelaus->lock);
+ return ret;
+}
+EXPORT_SYMBOL(menelaus_enable_slot);
+
int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_en)
{
int ret, val;
val = ret;
if (slot == 1) {
if (cd_en)
- val |= (1 << 4) | (1 << 6);
+ val |= MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN;
else
- val &= ~((1 << 4) | (1 << 6));
+ val &= ~(MCT_CTRL2_S1CD_BUFEN | MCT_CTRL2_S1CD_DBEN);
} else {
if (cd_en)
- val |= (1 << 5) | (1 << 7);
+ val |= MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN;
else
- val &= ~((1 << 5) | (1 << 7));
+ val &= ~(MCT_CTRL2_S2CD_BUFEN | MCT_CTRL2_S2CD_BEN);
}
ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, val);
if (ret < 0)
val = ret;
if (slot == 1) {
if (enable)
- val |= 1 << 0;
+ val |= MCT_CTRL3_SLOT1_EN;
else
- val &= ~(1 << 0);
+ val &= ~MCT_CTRL3_SLOT1_EN;
} else {
int b;
if (enable)
- ret |= 1 << 1;
+ val |= MCT_CTRL3_SLOT2_EN;
else
- ret &= ~(1 << 1);
+ val &= ~MCT_CTRL3_SLOT2_EN;
b = menelaus_read_reg(MENELAUS_MCT_CTRL2);
- b &= ~0x03;
+ b &= ~(MCT_CTRL2_VS2_SEL_D0 | MCT_CTRL2_VS2_SEL_D1);
b |= power;
ret = menelaus_write_reg(MENELAUS_MCT_CTRL2, b);
if (ret < 0)
goto out;
}
/* Disable autonomous shutdown */
- val &= ~(0x03 << 2);
+ val &= ~(MCT_CTRL3_S1_AUTO_EN | MCT_CTRL3_S2_AUTO_EN);
ret = menelaus_write_reg(MENELAUS_MCT_CTRL3, val);
out:
mutex_unlock(&the_menelaus->lock);
if (!the_menelaus->vcore_hw_mode) {
val = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
/* HW mode, turn OFF byte comparator */
- val |= ((1 << 7) | (1 << 5));
+ val |= (VCORE_CTRL1_HW_NSW | VCORE_CTRL1_BYP_COMP);
ret = menelaus_write_reg(MENELAUS_VCORE_CTRL1, val);
the_menelaus->vcore_hw_mode = 1;
}
ret = menelaus_read_reg(MENELAUS_GPIO_CTRL);
if (ret < 0)
goto out;
- t = ((1 << 6) | 0x04);
+ t = (GPIO_CTRL_SLPCTLEN | GPIO3_DIR_INPUT);
if (enable)
ret |= t;
else
static void menelaus_to_time(char *regs, struct rtc_time *t)
{
- t->tm_sec = BCD2BIN(regs[0]);
- t->tm_min = BCD2BIN(regs[1]);
+ t->tm_sec = bcd2bin(regs[0]);
+ t->tm_min = bcd2bin(regs[1]);
if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
- t->tm_hour = BCD2BIN(regs[2] & 0x1f) - 1;
+ t->tm_hour = bcd2bin(regs[2] & 0x1f) - 1;
if (regs[2] & RTC_HR_PM)
t->tm_hour += 12;
} else
- t->tm_hour = BCD2BIN(regs[2] & 0x3f);
- t->tm_mday = BCD2BIN(regs[3]);
- t->tm_mon = BCD2BIN(regs[4]) - 1;
- t->tm_year = BCD2BIN(regs[5]) + 100;
+ t->tm_hour = bcd2bin(regs[2] & 0x3f);
+ t->tm_mday = bcd2bin(regs[3]);
+ t->tm_mon = bcd2bin(regs[4]) - 1;
+ t->tm_year = bcd2bin(regs[5]) + 100;
}
static int time_to_menelaus(struct rtc_time *t, int regnum)
{
int hour, status;
- status = menelaus_write_reg(regnum++, BIN2BCD(t->tm_sec));
+ status = menelaus_write_reg(regnum++, bin2bcd(t->tm_sec));
if (status < 0)
goto fail;
- status = menelaus_write_reg(regnum++, BIN2BCD(t->tm_min));
+ status = menelaus_write_reg(regnum++, bin2bcd(t->tm_min));
if (status < 0)
goto fail;
if (the_menelaus->rtc_control & RTC_CTRL_MODE12) {
hour = t->tm_hour + 1;
if (hour > 12)
- hour = RTC_HR_PM | BIN2BCD(hour - 12);
+ hour = RTC_HR_PM | bin2bcd(hour - 12);
else
- hour = BIN2BCD(hour);
+ hour = bin2bcd(hour);
} else
- hour = BIN2BCD(t->tm_hour);
+ hour = bin2bcd(t->tm_hour);
status = menelaus_write_reg(regnum++, hour);
if (status < 0)
goto fail;
- status = menelaus_write_reg(regnum++, BIN2BCD(t->tm_mday));
+ status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mday));
if (status < 0)
goto fail;
- status = menelaus_write_reg(regnum++, BIN2BCD(t->tm_mon + 1));
+ status = menelaus_write_reg(regnum++, bin2bcd(t->tm_mon + 1));
if (status < 0)
goto fail;
- status = menelaus_write_reg(regnum++, BIN2BCD(t->tm_year - 100));
+ status = menelaus_write_reg(regnum++, bin2bcd(t->tm_year - 100));
if (status < 0)
goto fail;
}
menelaus_to_time(regs, t);
- t->tm_wday = BCD2BIN(regs[6]);
+ t->tm_wday = bcd2bin(regs[6]);
return 0;
}
status = time_to_menelaus(t, MENELAUS_RTC_SEC);
if (status < 0)
return status;
- status = menelaus_write_reg(MENELAUS_RTC_WKDAY, BIN2BCD(t->tm_wday));
+ status = menelaus_write_reg(MENELAUS_RTC_WKDAY, bin2bcd(t->tm_wday));
if (status < 0) {
- dev_err(&the_menelaus->client->dev, "rtc write reg %02x "
+ dev_err(&the_menelaus->client->dev, "rtc write reg %02x"
"err %d\n", MENELAUS_RTC_WKDAY, status);
return status;
}
/* If a true probe check the device */
rev = menelaus_read_reg(MENELAUS_REV);
if (rev < 0) {
- pr_err(DRIVER_NAME ": device not found");
+ dev_err(&client->dev, "device not found");
err = -ENODEV;
goto fail1;
}
err = request_irq(client->irq, menelaus_irq, IRQF_DISABLED,
DRIVER_NAME, menelaus);
if (err) {
- dev_dbg(&client->dev, "can't get IRQ %d, err %d\n",
+ dev_dbg(&client->dev, "can't get IRQ %d, err %d",
client->irq, err);
goto fail1;
}
mutex_init(&menelaus->lock);
INIT_WORK(&menelaus->work, menelaus_work);
- pr_info("Menelaus rev %d.%d\n", rev >> 4, rev & 0x0f);
+ dev_info(&client->dev, "Menelaus rev %d.%d\n", rev >> 4, rev & 0x0f);
val = menelaus_read_reg(MENELAUS_VCORE_CTRL1);
if (val < 0)
static int __init menelaus_init(void)
{
- int res;
-
- res = i2c_add_driver(&menelaus_i2c_driver);
- if (res < 0) {
- pr_err(DRIVER_NAME ": driver registration failed\n");
- return res;
- }
-
- return 0;
+ return i2c_add_driver(&menelaus_i2c_driver);
}
static void __exit menelaus_exit(void)
module will be called h3600_ts_input.
config TOUCHSCREEN_CORGI
- tristate "SharpSL (Corgi and Spitz series) touchscreen driver"
+ tristate "SharpSL (Corgi and Spitz series) touchscreen driver (DEPRECATED)"
depends on PXA_SHARPSL
+ select CORGI_SSP_DEPRECATED
default y
help
Say Y here to enable the driver for the touchscreen on the
To compile this driver as a module, choose M here: the
module will be called corgi_ts.
+ NOTE: this driver is deprecated, try enable SPI and generic
+ ADS7846-based touchscreen driver.
+
config TOUCHSCREEN_FUJITSU
tristate "Fujitsu serial touchscreen"
select SERIO
To compile this driver as a module, choose M here: the
module will be called atmel_tsadcc.
+config TOUCHSCREEN_TSC2005
+ tristate "TSC2005 touchscreen support"
+ depends on SPI_MASTER
+ help
+ Say Y here for if you are using the touchscreen features of TSC2005.
+
+config TOUCHSCREEN_TSC2102
+ tristate "TSC 2102 based touchscreens"
+ depends on SPI_MASTER
+ select SPI_TSC2102
+ help
+ Say Y here if you have a touchscreen interface using the
+ TI TSC 2102 controller, and your board-specific initialization
+ code includes that in its table of SPI devices. Also make
+ sure the proper SPI controller is selected.
+
+ If unsure, say N (but it's safe to say "Y").
+
+ To compile this driver as a module, choose M here: the
+ module will be called tsc2102_ts.
+
+config TOUCHSCREEN_TSC210X
+ tristate "TI TSC210x based touchscreens"
+ depends on SPI_MASTER
+ select SPI_TSC210X
+ help
+ Say Y here if you have a touchscreen interface using a
+ TI TSC210x controller, and your board-specific initialisation
+ code includes that in its table of SPI devices.
+
+ If unsure, say N (but it's safe to say "Y").
+
+ To compile this driver as a module, choose M here: the
+ module will be called tsc210x_ts.
+
+config TOUCHSCREEN_TSC2301
+ tristate "TSC2301 touchscreen support"
+ depends on SPI_TSC2301
+ help
+ Say Y here for if you are using the touchscreen features of TSC2301.
+
config TOUCHSCREEN_UCB1400
tristate "Philips UCB1400 touchscreen"
- select AC97_BUS
+ depends on AC97_BUS
+ depends on UCB1400_CORE
help
This enables support for the Philips UCB1400 touchscreen interface.
The UCB1400 is an AC97 audio codec. The touchscreen interface
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
+ #include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <asm/irq.h>
int ignore;
};
+ /*
+ * We allocate this separately to avoid cache line sharing issues when
+ * driver is used with DMA-based SPI controllers (like atmel_spi) on
+ * systems where main memory is not DMA-coherent (most non-x86 boards).
+ */
+ struct ads7846_packet {
+ u8 read_x, read_y, read_z1, read_z2, pwrdown;
+ u16 dummy; /* for the pwrdown read */
+ struct ts_event tc;
+ };
+
struct ads7846 {
struct input_dev *input;
char phys[32];
u16 x_plate_ohms;
u16 pressure_max;
- u8 read_x, read_y, read_z1, read_z2, pwrdown;
- u16 dummy; /* for the pwrdown read */
- struct ts_event tc;
+ struct ads7846_packet *packet;
struct spi_transfer xfer[18];
struct spi_message msg[5];
void *filter_data;
void (*filter_cleanup)(void *data);
int (*get_pendown_state)(void);
+ int gpio_pendown;
};
/* leave chip selected when we're done, for quicker re-select? */
const char *buf, size_t count)
{
struct ads7846 *ts = dev_get_drvdata(dev);
- char *endp;
- int i;
+ long i;
+
+ if (strict_strtoul(buf, 10, &i))
+ return -EINVAL;
- i = simple_strtoul(buf, &endp, 10);
spin_lock_irq(&ts->lock);
if (i)
/*--------------------------------------------------------------------------*/
+ static int get_pendown_state(struct ads7846 *ts)
+ {
+ if (ts->get_pendown_state)
+ return ts->get_pendown_state();
+
+ return !gpio_get_value(ts->gpio_pendown);
+ }
+
/*
* PENIRQ only kicks the timer. The timer only reissues the SPI transfer,
* to retrieve touchscreen status.
static void ads7846_rx(void *ads)
{
struct ads7846 *ts = ads;
+ struct ads7846_packet *packet = ts->packet;
unsigned Rt;
u16 x, y, z1, z2;
/* ads7846_rx_val() did in-place conversion (including byteswap) from
* on-the-wire format as part of debouncing to get stable readings.
*/
- x = ts->tc.x;
- y = ts->tc.y;
- z1 = ts->tc.z1;
- z2 = ts->tc.z2;
+ x = packet->tc.x;
+ y = packet->tc.y;
+ z1 = packet->tc.z1;
+ z2 = packet->tc.z2;
/* range filtering */
if (x == MAX_12BIT)
* the maximum. Don't report it to user space, repeat at least
* once more the measurement
*/
- if (ts->tc.ignore || Rt > ts->pressure_max) {
+ if (packet->tc.ignore || Rt > ts->pressure_max) {
#ifdef VERBOSE
pr_debug("%s: ignored %d pressure %d\n",
- ts->spi->dev.bus_id, ts->tc.ignore, Rt);
+ ts->spi->dev.bus_id, packet->tc.ignore, Rt);
#endif
hrtimer_start(&ts->timer, ktime_set(0, TS_POLL_PERIOD),
HRTIMER_MODE_REL);
*/
if (ts->penirq_recheck_delay_usecs) {
udelay(ts->penirq_recheck_delay_usecs);
- if (!ts->get_pendown_state())
+ if (!get_pendown_state(ts))
Rt = 0;
}
static void ads7846_rx_val(void *ads)
{
struct ads7846 *ts = ads;
+ struct ads7846_packet *packet = ts->packet;
struct spi_message *m;
struct spi_transfer *t;
int val;
case ADS7846_FILTER_REPEAT:
break;
case ADS7846_FILTER_IGNORE:
- ts->tc.ignore = 1;
+ packet->tc.ignore = 1;
/* Last message will contain ads7846_rx() as the
* completion function.
*/
break;
case ADS7846_FILTER_OK:
*(u16 *)t->rx_buf = val;
- ts->tc.ignore = 0;
+ packet->tc.ignore = 0;
m = &ts->msg[++ts->msg_idx];
break;
default:
spin_lock_irq(&ts->lock);
- if (unlikely(!ts->get_pendown_state() ||
+ if (unlikely(!get_pendown_state(ts) ||
device_suspended(&ts->spi->dev))) {
if (ts->pendown) {
struct input_dev *input = ts->input;
unsigned long flags;
spin_lock_irqsave(&ts->lock, flags);
- if (likely(ts->get_pendown_state())) {
+ if (likely(get_pendown_state(ts))) {
if (!ts->irq_disabled) {
/* The ARM do_simple_IRQ() dispatcher doesn't act
* like the other dispatchers: it will report IRQs
/* we know the chip's in lowpower mode since we always
* leave it that way after every request
*/
-
}
/* Must be called with ts->lock held */
return 0;
}
+ static int __devinit setup_pendown(struct spi_device *spi, struct ads7846 *ts)
+ {
+ struct ads7846_platform_data *pdata = spi->dev.platform_data;
+ int err;
+
+ /* REVISIT when the irq can be triggered active-low, or if for some
+ * reason the touchscreen isn't hooked up, we don't need to access
+ * the pendown state.
+ */
+ if (!pdata->get_pendown_state && !gpio_is_valid(pdata->gpio_pendown)) {
+ dev_err(&spi->dev, "no get_pendown_state nor gpio_pendown?\n");
+ return -EINVAL;
+ }
+
+ if (pdata->get_pendown_state) {
+ ts->get_pendown_state = pdata->get_pendown_state;
+ return 0;
+ }
+
+ err = gpio_request(pdata->gpio_pendown, "ads7846_pendown");
+ if (err) {
+ dev_err(&spi->dev, "failed to request pendown GPIO%d\n",
+ pdata->gpio_pendown);
+ return err;
+ }
+
+ ts->gpio_pendown = pdata->gpio_pendown;
+ return 0;
+ }
+
static int __devinit ads7846_probe(struct spi_device *spi)
{
struct ads7846 *ts;
+ struct ads7846_packet *packet;
struct input_dev *input_dev;
struct ads7846_platform_data *pdata = spi->dev.platform_data;
struct spi_message *m;
return -ENODEV;
}
+ /* enable voltage */
+ if (pdata->vaux_control != NULL) {
+ err = pdata->vaux_control(VAUX_ENABLE);
+ if (err != 0) {
+ dev_dbg(&spi->dev, "TS vaux enable failed\n");
+ return err;
+ }
+ }
+
/* don't exceed max specified sample rate */
if (spi->max_speed_hz > (125000 * SAMPLE_BITS)) {
dev_dbg(&spi->dev, "f(sample) %d KHz?\n",
return -EINVAL;
}
- /* REVISIT when the irq can be triggered active-low, or if for some
- * reason the touchscreen isn't hooked up, we don't need to access
- * the pendown state.
- */
- if (pdata->get_pendown_state == NULL) {
- dev_dbg(&spi->dev, "no get_pendown_state function?\n");
- return -EINVAL;
- }
-
/* We'd set TX wordsize 8 bits and RX wordsize to 13 bits ... except
* that even if the hardware can do that, the SPI controller driver
* may not. So we stick to very-portable 8 bit words, both RX and TX.
return err;
ts = kzalloc(sizeof(struct ads7846), GFP_KERNEL);
+ packet = kzalloc(sizeof(struct ads7846_packet), GFP_KERNEL);
input_dev = input_allocate_device();
- if (!ts || !input_dev) {
+ if (!ts || !packet || !input_dev) {
err = -ENOMEM;
goto err_free_mem;
}
dev_set_drvdata(&spi->dev, ts);
+ ts->packet = packet;
ts->spi = spi;
ts->input = input_dev;
ts->vref_mv = pdata->vref_mv;
ts->filter_data = ts;
} else
ts->filter = ads7846_no_filter;
- ts->get_pendown_state = pdata->get_pendown_state;
+
+ err = setup_pendown(spi, ts);
+ if (err)
+ goto err_cleanup_filter;
if (pdata->penirq_recheck_delay_usecs)
ts->penirq_recheck_delay_usecs =
spi_message_init(m);
/* y- still on; turn on only y+ (and ADC) */
- ts->read_y = READ_Y(vref);
- x->tx_buf = &ts->read_y;
+ packet->read_y = READ_Y(vref);
+ x->tx_buf = &packet->read_y;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.y;
+ x->rx_buf = &packet->tc.y;
x->len = 2;
spi_message_add_tail(x, m);
x->delay_usecs = pdata->settle_delay_usecs;
x++;
- x->tx_buf = &ts->read_y;
+ x->tx_buf = &packet->read_y;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.y;
+ x->rx_buf = &packet->tc.y;
x->len = 2;
spi_message_add_tail(x, m);
}
/* turn y- off, x+ on, then leave in lowpower */
x++;
- ts->read_x = READ_X(vref);
- x->tx_buf = &ts->read_x;
+ packet->read_x = READ_X(vref);
+ x->tx_buf = &packet->read_x;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.x;
+ x->rx_buf = &packet->tc.x;
x->len = 2;
spi_message_add_tail(x, m);
x->delay_usecs = pdata->settle_delay_usecs;
x++;
- x->tx_buf = &ts->read_x;
+ x->tx_buf = &packet->read_x;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.x;
+ x->rx_buf = &packet->tc.x;
x->len = 2;
spi_message_add_tail(x, m);
}
spi_message_init(m);
x++;
- ts->read_z1 = READ_Z1(vref);
- x->tx_buf = &ts->read_z1;
+ packet->read_z1 = READ_Z1(vref);
+ x->tx_buf = &packet->read_z1;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.z1;
+ x->rx_buf = &packet->tc.z1;
x->len = 2;
spi_message_add_tail(x, m);
x->delay_usecs = pdata->settle_delay_usecs;
x++;
- x->tx_buf = &ts->read_z1;
+ x->tx_buf = &packet->read_z1;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.z1;
+ x->rx_buf = &packet->tc.z1;
x->len = 2;
spi_message_add_tail(x, m);
}
spi_message_init(m);
x++;
- ts->read_z2 = READ_Z2(vref);
- x->tx_buf = &ts->read_z2;
+ packet->read_z2 = READ_Z2(vref);
+ x->tx_buf = &packet->read_z2;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.z2;
+ x->rx_buf = &packet->tc.z2;
x->len = 2;
spi_message_add_tail(x, m);
x->delay_usecs = pdata->settle_delay_usecs;
x++;
- x->tx_buf = &ts->read_z2;
+ x->tx_buf = &packet->read_z2;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->tc.z2;
+ x->rx_buf = &packet->tc.z2;
x->len = 2;
spi_message_add_tail(x, m);
}
spi_message_init(m);
x++;
- ts->pwrdown = PWRDOWN;
- x->tx_buf = &ts->pwrdown;
+ packet->pwrdown = PWRDOWN;
+ x->tx_buf = &packet->pwrdown;
x->len = 1;
spi_message_add_tail(x, m);
x++;
- x->rx_buf = &ts->dummy;
+ x->rx_buf = &packet->dummy;
x->len = 2;
CS_CHANGE(*x);
spi_message_add_tail(x, m);
spi->dev.driver->name, ts)) {
dev_dbg(&spi->dev, "irq %d busy?\n", spi->irq);
err = -EBUSY;
- goto err_cleanup_filter;
+ goto err_free_gpio;
}
err = ads784x_hwmon_register(spi, ts);
ads784x_hwmon_unregister(spi, ts);
err_free_irq:
free_irq(spi->irq, ts);
+ err_free_gpio:
+ if (ts->gpio_pendown != -1)
+ gpio_free(ts->gpio_pendown);
err_cleanup_filter:
if (ts->filter_cleanup)
ts->filter_cleanup(ts->filter_data);
err_free_mem:
input_free_device(input_dev);
+ kfree(packet);
kfree(ts);
return err;
}
/* suspend left the IRQ disabled */
enable_irq(ts->spi->irq);
+ if (ts->gpio_pendown != -1)
+ gpio_free(ts->gpio_pendown);
+
if (ts->filter_cleanup)
ts->filter_cleanup(ts->filter_data);
+ kfree(ts->packet);
kfree(ts);
dev_dbg(&spi->dev, "unregistered touchscreen\n");
This option enables support for LEDs driven using outputs
of the dedicated PWM controller found on newer Atmel SOCs.
- config LEDS_CORGI
- tristate "LED Support for the Sharp SL-C7x0 series"
- depends on LEDS_CLASS && PXA_SHARP_C7xx
- help
- This option enables support for the LEDs on Sharp Zaurus
- SL-C7x0 series (C700, C750, C760, C860).
-
config LEDS_LOCOMO
tristate "LED Support for Locomo device"
depends on LEDS_CLASS && SHARP_LOCOMO
This option enables support for the LEDs on Sharp Locomo.
Zaurus models SL-5500 and SL-5600.
- config LEDS_SPITZ
- tristate "LED Support for the Sharp SL-Cxx00 series"
- depends on LEDS_CLASS && PXA_SHARP_Cxx00
- help
- This option enables support for the LEDs on Sharp Zaurus
- SL-Cxx00 series (C1000, C3000, C3100).
-
config LEDS_S3C24XX
tristate "LED Support for Samsung S3C24XX GPIO LEDs"
depends on LEDS_CLASS && ARCH_S3C2410
help
This option enables support for the PCEngines WRAP programmable LEDs.
+config LEDS_OMAP_DEBUG
+ boolean "LED Support for OMAP debug board LEDs"
+ depends on LEDS_CLASS=y && ARCH_OMAP
+ help
+ Enables support for the LEDs on the debug board used with OMAP
+ reference boards like H2/H3/H4 and Perseus2. Up to six of these
+ may be claimed by the original ARM debug LED API.
+
+config LEDS_OMAP
+ tristate "LED Support for OMAP GPIO LEDs"
+ depends on LEDS_CLASS && ARCH_OMAP
+ help
+ This option enables support for the LEDs on OMAP processors.
+
+config LEDS_OMAP_PWM
+ tristate "LED Support for OMAP PWM-controlled LEDs"
+ depends on LEDS_CLASS && ARCH_OMAP && OMAP_DM_TIMER
+ help
+ This options enables support for LEDs connected to GPIO lines
+ controlled by a PWM timer on OMAP CPUs.
+
config LEDS_H1940
tristate "LED Support for iPAQ H1940 device"
depends on LEDS_CLASS && ARCH_H1940
help
This option enables support for the Cobalt Raq series LEDs.
+ config LEDS_SUNFIRE
+ tristate "LED support for SunFire servers."
+ depends on LEDS_CLASS && SPARC64
+ select LEDS_TRIGGERS
+ help
+ This option enables support for the Left, Middle, and Right
+ LEDs on the I/O and CPU boards of SunFire UltraSPARC servers.
+
config LEDS_HP6XX
tristate "LED Support for the HP Jornada 6xx"
depends on LEDS_CLASS && SH_HP6XX
outputs. To be useful the particular board must have LEDs
and they must be connected to the GPIO lines.
- config LEDS_CM_X270
- tristate "LED Support for the CM-X270 LEDs"
- depends on LEDS_CLASS && MACH_ARMCORE
+ config LEDS_HP_DISK
+ tristate "LED Support for disk protection LED on HP notebooks"
+ depends on LEDS_CLASS && ACPI
help
- This option enables support for the CM-X270 LEDs.
+ This option enable support for disk protection LED, found on
+ newer HP notebooks.
config LEDS_CLEVO_MAIL
tristate "Mail LED on Clevo notebook (EXPERIMENTAL)"
LED driver chips accessed via the I2C bus. Supported
devices include PCA9550, PCA9551, PCA9552, and PCA9553.
+ config LEDS_DA903X
+ tristate "LED Support for DA9030/DA9034 PMIC"
+ depends on LEDS_CLASS && PMIC_DA903X
+ help
+ This option enables support for on-chip LED drivers found
+ on Dialog Semiconductor DA9030/DA9034 PMICs.
+
comment "LED Triggers"
config LEDS_TRIGGERS
config LEDS_TRIGGER_IDE_DISK
bool "LED IDE Disk Trigger"
- depends on LEDS_TRIGGERS && BLK_DEV_IDEDISK
+ depends on LEDS_TRIGGERS && IDE_GD_ATA
help
This allows LEDs to be controlled by IDE disk activity.
If unsure, say Y.
load average.
If unsure, say Y.
+ config LEDS_TRIGGER_BACKLIGHT
+ tristate "LED backlight Trigger"
+ depends on LEDS_TRIGGERS
+ help
+ This allows LEDs to be controlled as a backlight device: they
+ turn off and on when the display is blanked and unblanked.
+
+ If unsure, say N.
+
config LEDS_TRIGGER_DEFAULT_ON
tristate "LED Default ON Trigger"
depends on LEDS_TRIGGERS
# LED Platform Drivers
obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o
- obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o
obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o
- obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o
obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
obj-$(CONFIG_LEDS_AMS_DELTA) += leds-ams-delta.o
obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o
obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
+obj-$(CONFIG_LEDS_OMAP) += leds-omap.o
+obj-$(CONFIG_LEDS_OMAP_PWM) += leds-omap-pwm.o
obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o
obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
+ obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
obj-$(CONFIG_LEDS_PCA9532) += leds-pca9532.o
obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
- obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o
obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o
obj-$(CONFIG_LEDS_FSG) += leds-fsg.o
obj-$(CONFIG_LEDS_PCA955X) += leds-pca955x.o
+ obj-$(CONFIG_LEDS_DA903X) += leds-da903x.o
+ obj-$(CONFIG_LEDS_HP_DISK) += leds-hp-disk.o
# LED Triggers
obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
obj-$(CONFIG_LEDS_TRIGGER_IDE_DISK) += ledtrig-ide-disk.o
obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT) += ledtrig-heartbeat.o
+ obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT) += ledtrig-backlight.o
obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o
help
Enter the I/O port of your Zoltrix radio card.
+config RADIO_TEA5761
+ tristate "Philips Semiconductors TEA5761 I2C FM Radio"
+ help
+ Choose Y here if you have one of these AM/FM radio cards.
+
+ In order to control your radio card, you will need to use programs
+ that are compatible with the Video For Linux 2 API. Information on
+ this API and pointers to "v4l" programs may be found at
+ <file:Documentation/video4linux/API.html>.
+
+ To compile this driver as a module, choose M here: the
+ module will be called radio-tea5761.
+
config USB_DSBR
tristate "D-Link/GemTek USB FM radio support"
depends on USB && VIDEO_V4L2
computer's USB port.
To compile this driver as a module, choose M here: the
- module will be called radio-silabs.
+ module will be called radio-si470x.
+
+ config USB_MR800
+ tristate "AverMedia MR 800 USB FM radio support"
+ depends on USB && VIDEO_V4L2
+ ---help---
+ Say Y here if you want to connect this type of radio to your
+ computer's USB port. Note that the audio is not digital, and
+ you must connect the line out connector to a sound card or a
+ set of speakers.
+
+ To compile this driver as a module, choose M here: the
+ module will be called radio-mr800.
endif # RADIO_ADAPTERS
obj-$(CONFIG_RADIO_GEMTEK_PCI) += radio-gemtek-pci.o
obj-$(CONFIG_RADIO_TRUST) += radio-trust.o
obj-$(CONFIG_RADIO_MAESTRO) += radio-maestro.o
+obj-$(CONFIG_RADIO_TEA5761) += radio-tea5761.o
obj-$(CONFIG_USB_DSBR) += dsbr100.o
obj-$(CONFIG_USB_SI470X) += radio-si470x.o
+ obj-$(CONFIG_USB_MR800) += radio-mr800.o
EXTRA_CFLAGS += -Isound
# Makefile for the video capture/playback device drivers.
#
- zr36067-objs := zoran_procfs.o zoran_device.o \
- zoran_driver.o zoran_card.o
tuner-objs := tuner-core.o
msp3400-objs := msp3400-driver.o msp3400-kthreads.o
obj-$(CONFIG_VIDEO_BT866) += bt866.o
obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
- obj-$(CONFIG_VIDEO_ZORAN) += zr36067.o videocodec.o
- obj-$(CONFIG_VIDEO_ZORAN_DC30) += zr36050.o zr36016.o
- obj-$(CONFIG_VIDEO_ZORAN_ZR36060) += zr36060.o
+ obj-$(CONFIG_VIDEO_ZORAN) += zoran/
obj-$(CONFIG_VIDEO_PMS) += pms.o
obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o
obj-$(CONFIG_VIDEO_MXB) += mxb.o
obj-$(CONFIG_VIDEO_HEXIUM_ORION) += hexium_orion.o
obj-$(CONFIG_VIDEO_HEXIUM_GEMINI) += hexium_gemini.o
- obj-$(CONFIG_VIDEO_DPC) += dpc7146.o
- obj-$(CONFIG_TUNER_3036) += tuner-3036.o
obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o
obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o
obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o
+obj-$(CONFIG_VIDEO_OMAP_CAMERA) += omap/
obj-$(CONFIG_VIDEO_CX25840) += cx25840/
obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o
obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
+obj-$(CONFIG_VIDEO_OMAP2) += omap24xxcam.o omap24xxcam-dma.o
obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
+obj-$(CONFIG_VIDEO_OV9640) += ov9640.o
obj-$(CONFIG_USB_DABUSB) += dabusb.o
obj-$(CONFIG_USB_OV511) += ov511.o
obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o
obj-$(CONFIG_SOC_CAMERA) += soc_camera.o
obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o
+ obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o
obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o
obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o
HTC Magician devices, respectively. Actual functionality is
handled by the leds-pasic3 and ds1wm drivers.
+ config UCB1400_CORE
+ tristate "Philips UCB1400 Core driver"
+ depends on AC97_BUS
+ depends on GPIOLIB
+ help
+ This enables support for the Philips UCB1400 core functions.
+ The UCB1400 is an AC97 audio codec.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ucb1400_core.
+
config TWL4030_CORE
bool "Texas Instruments TWL4030/TPS659x0 Support"
depends on I2C=y && GENERIC_HARDIRQS && (ARCH_OMAP2 || ARCH_OMAP3)
high speed USB OTG transceiver, an audio codec (on most
versions) and many other features.
+config TWL4030_POWER
+ bool "Support power sequencing scripts on TWL4030/TPS659x0"
+ depends on TWL4030_CORE
+ help
+ Say yes here if you want to use the power sequencing scripts on
+ the TWL4030/TPS659x0. These scripts control which regulators or
+ oscillators are switched off or on or reset when a sleep, wakeup
+ or warm reset event occurs.
+
config MFD_TMIO
bool
default n
help
Support for Toshiba Mobile IO Controller TC6393XB
+ config MFD_WM8400
+ tristate "Support Wolfson Microelectronics WM8400"
+ help
+ Support for the Wolfson Microelecronics WM8400 PMIC and audio
+ CODEC. This driver adds provides common support for accessing
+ the device, additional drivers must be enabled in order to use
+ the functionality of the device.
+
+ config MFD_WM8350
+ tristate
+
+ config MFD_WM8350_CONFIG_MODE_0
+ bool
+ depends on MFD_WM8350
+
+ config MFD_WM8350_CONFIG_MODE_1
+ bool
+ depends on MFD_WM8350
+
+ config MFD_WM8350_CONFIG_MODE_2
+ bool
+ depends on MFD_WM8350
+
+ config MFD_WM8350_CONFIG_MODE_3
+ bool
+ depends on MFD_WM8350
+
+ config MFD_WM8350_I2C
+ tristate "Support Wolfson Microelectronics WM8350 with I2C"
+ select MFD_WM8350
+ depends on I2C
+ help
+ The WM8350 is an integrated audio and power management
+ subsystem with watchdog and RTC functionality for embedded
+ systems. This option enables core support for the WM8350 with
+ I2C as the control interface. Additional options must be
+ selected to enable support for the functionality of the chip.
+
endmenu
menu "Multimedia Capabilities Port drivers"
obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o
obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o
+ obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
+ wm8350-objs := wm8350-core.o wm8350-regmap.o wm8350-gpio.o
+ obj-$(CONFIG_MFD_WM8350) += wm8350.o
+ obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o
+
obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
+obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o
obj-$(CONFIG_MFD_CORE) += mfd-core.o
ifeq ($(CONFIG_SA1100_ASSABET),y)
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o
endif
+ obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o
config ATMEL_PWM
tristate "Atmel AT32/AT91 PWM support"
- depends on AVR32 || ARCH_AT91
+ depends on AVR32 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9
help
This option enables device driver support for the PWM channels
on certain Atmel prcoessors. Pulse Width Modulation is used for
depends on NEW_LEDS
depends on BACKLIGHT_CLASS_DEVICE
depends on SERIO_I8042
+ depends on RFKILL
select ACPI_WMI
---help---
This is a driver for newer Acer (and Wistron) laptops. It adds
If you have an MSI S270 laptop, say Y or M here.
+ config PANASONIC_LAPTOP
+ tristate "Panasonic Laptop Extras"
+ depends on X86 && INPUT && ACPI
+ depends on BACKLIGHT_CLASS_DEVICE
+ ---help---
+ This driver adds support for access to backlight control and hotkeys
+ on Panasonic Let's Note laptops.
+
+ If you have a Panasonic Let's note laptop (such as the R1(N variant),
+ R2, R3, R5, T2, W2 and Y2 series), say Y.
+
config COMPAL_LAPTOP
tristate "Compal Laptop Extras"
depends on X86
depends on BACKLIGHT_CLASS_DEVICE
depends on HWMON
depends on EXPERIMENTAL
-
+ depends on RFKILL
---help---
This driver supports the Fn-Fx keys on Eee PC laptops.
It also adds the ability to switch camera/wlan on/off.
- If you have an Eee PC laptop, say Y or M here.
+config OMAP_STI
+ bool "Serial Trace Interface support"
+ depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
+ default n
+ help
+ Serial Trace Interface. The protocols suported for OMAP1/2/3 are
+ STI/CSTI/XTIv2 correspondingly.
+
+config OMAP_STI_CONSOLE
+ bool "STI console support"
+ depends on OMAP_STI
+ help
+ This enables a console driver by way of STI/XTI.
config ENCLOSURE_SERVICES
tristate "Enclosure Services"
obj-$(CONFIG_IBM_ASM) += ibmasm/
obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
+obj-$(CONFIG_OMAP_STI) += sti/
obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
obj-$(CONFIG_EEEPC_LAPTOP) += eeepc-laptop.o
obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
obj-$(CONFIG_SONY_LAPTOP) += sony-laptop.o
obj-$(CONFIG_THINKPAD_ACPI) += thinkpad_acpi.o
obj-$(CONFIG_FUJITSU_LAPTOP) += fujitsu-laptop.o
+ obj-$(CONFIG_PANASONIC_LAPTOP) += panasonic-laptop.o
obj-$(CONFIG_EEPROM_93CX6) += eeprom_93cx6.o
obj-$(CONFIG_INTEL_MENLOW) += intel_menlow.o
obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
# MMC/SD host controller drivers
#
- comment "MMC/SD Host Controller Drivers"
+ comment "MMC/SD/SDIO Host Controller Drivers"
config MMC_ARMMMCI
tristate "ARM AMBA Multimedia Card Interface support"
config MMC_OMAP
tristate "TI OMAP Multimedia Card Interface support"
- depends on ARCH_OMAP
+ depends on ARCH_OMAP1 || (ARCH_OMAP2 && ARCH_OMAP2420)
select TPS65010 if MACH_OMAP_H2
+ select OMAP_GPIO_SWITCH if MACH_NOKIA_N800
help
This selects the TI OMAP Multimedia card Interface.
If you have an OMAP board with a Multimedia Card slot,
If unsure, say N.
+config MMC_OMAP_HS
+ tristate "TI OMAP High Speed Multimedia Card Interface support"
+ depends on (ARCH_OMAP2 && ARCH_OMAP2430) || ARCH_OMAP3
+ select TWL4030_CORE if MACH_OMAP_2430SDP || MACH_OMAP_3430SDP
+ help
+ This selects the TI OMAP High Speed Multimedia card Interface.
+ If you have an OMAP2(2430) or OMAP3 board with a Multimedia Card slot,
+ say Y or M here.
+
+ If unsure, say N.
+
config MMC_WBSD
tristate "Winbond W83L51xD SD/MMC Card Interface support"
depends on ISA_DMA_API
If unsure, say N.
+ config MMC_ATMELMCI_DMA
+ bool "Atmel MCI DMA support (EXPERIMENTAL)"
+ depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL
+ help
+ Say Y here to have the Atmel MCI driver use a DMA engine to
+ do data transfers and thus increase the throughput and
+ reduce the CPU utilization. Note that this is highly
+ experimental and may cause the driver to lock up.
+
+ If unsure, say N.
+
config MMC_IMX
tristate "Motorola i.MX Multimedia Card Interface support"
depends on ARCH_IMX
module will be called tifm_sd.
config MMC_SPI
- tristate "MMC/SD over SPI"
- depends on MMC && SPI_MASTER && !HIGHMEM && HAS_DMA
+ tristate "MMC/SD/SDIO over SPI"
+ depends on SPI_MASTER && !HIGHMEM && HAS_DMA
select CRC7
select CRC_ITU_T
help
- Some systems accss MMC/SD cards using a SPI controller instead of
- using a "native" MMC/SD controller. This has a disadvantage of
- being relatively high overhead, but a compensating advantage of
- working on many systems without dedicated MMC/SD controllers.
+ Some systems accss MMC/SD/SDIO cards using a SPI controller
+ instead of using a "native" MMC/SD/SDIO controller. This has a
+ disadvantage of being relatively high overhead, but a compensating
+ advantage of working on many systems without dedicated MMC/SD/SDIO
+ controllers.
If unsure, or if your system has no SPI master driver, say N.
config MMC_S3C
tristate "Samsung S3C SD/MMC Card Interface support"
- depends on ARCH_S3C2410 && MMC
+ depends on ARCH_S3C2410
help
This selects a driver for the MCI interface found in
Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs.
config MMC_SDRICOH_CS
tristate "MMC/SD driver for Ricoh Bay1Controllers (EXPERIMENTAL)"
- depends on EXPERIMENTAL && MMC && PCI && PCMCIA
+ depends on EXPERIMENTAL && PCI && PCMCIA
help
Say Y here if your Notebook reports a Ricoh Bay1Controller PCMCIA
card whenever you insert a MMC or SD card into the card slot.
*
* mtdparts=<mtddef>[;<mtddef]
* <mtddef> := <mtd-id>:<partdef>[,<partdef>]
+ * where <mtd-id> is the name from the "cat /proc/mtd" command
* <partdef> := <size>[@offset][<name>][ro][lk]
* <mtd-id> := unique name used in mapping driver/device (mtd->name)
* <size> := standard linux memsize OR "-" to denote all remaining space
*
* This function needs to be visible for bootloaders.
*/
-static int mtdpart_setup(char *s)
+int mtdpart_setup(char *s)
{
cmdline = s;
return 1;
Mapping for the Flaga digital module. If you don't have one, ignore
this setting.
- config MTD_WALNUT
- tristate "Flash device mapped on IBM 405GP Walnut"
- depends on MTD_JEDECPROBE && WALNUT && !PPC_MERGE
- help
- This enables access routines for the flash chips on the IBM 405GP
- Walnut board. If you have one of these boards and would like to
- use the flash chips on it, say 'Y'.
-
- config MTD_EBONY
- tristate "Flash devices mapped on IBM 440GP Ebony"
- depends on MTD_JEDECPROBE && EBONY && !PPC_MERGE
- help
- This enables access routines for the flash chips on the IBM 440GP
- Ebony board. If you have one of these boards and would like to
- use the flash chips on it, say 'Y'.
-
- config MTD_OCOTEA
- tristate "Flash devices mapped on IBM 440GX Ocotea"
- depends on MTD_CFI && OCOTEA && !PPC_MERGE
- help
- This enables access routines for the flash chips on the IBM 440GX
- Ocotea board. If you have one of these boards and would like to
- use the flash chips on it, say 'Y'.
-
config MTD_REDWOOD
tristate "CFI Flash devices mapped on IBM Redwood"
depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
PhotoMax Digital Picture Frame.
If you have such a device, say 'Y'.
+config MTD_NOR_TOTO
+ tristate "NOR Flash device on TOTO board"
+ depends on ARCH_OMAP && OMAP_TOTO
+ help
+ This enables access to the NOR flash on the Texas Instruments
+ TOTO board.
+
config MTD_H720X
tristate "Hynix evaluation board mappings"
depends on MTD_CFI && ( ARCH_H7201 || ARCH_H7202 )
config MTD_UCLINUX
tristate "Generic uClinux RAM/ROM filesystem support"
- depends on MTD_PARTITIONS && !MMU
+ depends on MTD_PARTITIONS && MTD_RAM && !MMU
help
Map driver to support image based filesystems for uClinux.
obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
obj-$(CONFIG_MTD_NETtel) += nettel.o
obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
- obj-$(CONFIG_MTD_EBONY) += ebony.o
- obj-$(CONFIG_MTD_OCOTEA) += ocotea.o
- obj-$(CONFIG_MTD_WALNUT) += walnut.o
obj-$(CONFIG_MTD_H720X) += h720x-flash.o
obj-$(CONFIG_MTD_SBC8240) += sbc8240.o
+obj-$(CONFIG_MTD_NOR_TOTO) += omap-toto-flash.o
obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
help
This enables the driver for the iPAQ h1900 flash.
+ config MTD_NAND_GPIO
+ tristate "GPIO NAND Flash driver"
+ depends on GENERIC_GPIO && ARM
+ help
+ This enables a GPIO based NAND flash driver.
+
config MTD_NAND_SPIA
tristate "NAND Flash device on SPIA board"
depends on ARCH_P720T
help
Support for NAND flash on Amstrad E3 (Delta).
+config MTD_NAND_OMAP2
+ tristate "NAND Flash device on OMAP2 and OMAP3"
+ depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3)
+ help
+ Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
+
+config MTD_NAND_OMAP
+ tristate "NAND Flash device on OMAP H3/H2/P2 boards"
+ depends on ARM && ARCH_OMAP1 && MTD_NAND && (MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_PERSEUS2)
+ help
+ Support for NAND flash on Texas Instruments H3/H2/P2 platforms.
+
+config MTD_NAND_OMAP_HW
+ bool "OMAP HW NAND Flash controller support"
+ depends on ARM && ARCH_OMAP16XX && MTD_NAND
+
+ help
+ Driver for TI OMAP16xx hardware NAND flash controller.
+
+config MTD_NAND_TOTO
+ tristate "NAND Flash device on TOTO board"
+ depends on ARCH_OMAP && BROKEN
+ help
+ Support for NAND flash on Texas Instruments Toto platform.
+
config MTD_NAND_TS7250
tristate "NAND Flash device on TS-7250 board"
depends on MACH_TS72XX
incorrect ECC generation, and if using these, the default of
software ECC is preferable.
- config MTD_NAND_NDFC
- tristate "NDFC NanD Flash Controller"
- depends on 4xx && !PPC_MERGE
- select MTD_NAND_ECC_SMC
- help
- NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
-
config MTD_NAND_S3C2410_CLKSTOP
bool "S3C2410 NAND IDLE clock stop"
depends on MTD_NAND_S3C2410
This enables the driver for the NAND flash device found on
PXA3xx processors
+ config MTD_NAND_PXA3xx_BUILTIN
+ bool "Use builtin definitions for some NAND chips (deprecated)"
+ depends on MTD_NAND_PXA3xx
+ help
+ This enables builtin definitions for some NAND chips. This
+ is deprecated in favor of platform specific data.
+
config MTD_NAND_CM_X270
tristate "Support for NAND Flash on CM-X270 modules"
depends on MTD_NAND && MACH_ARMCORE
config MTD_NAND_FSL_UPM
tristate "Support for NAND on Freescale UPM"
- depends on MTD_NAND && OF_GPIO && (PPC_83xx || PPC_85xx)
+ depends on MTD_NAND && (PPC_83xx || PPC_85xx)
select FSL_LBC
help
Enables support for NAND Flash chips wired onto Freescale PowerPC
processor localbus with User-Programmable Machine support.
+ config MTD_NAND_MXC
+ tristate "MXC NAND support"
+ depends on ARCH_MX2
+ help
+ This enables the driver for the NAND flash controller on the
+ MXC processors.
+
+ config MTD_NAND_SH_FLCTL
+ tristate "Support for NAND on Renesas SuperH FLCTL"
+ depends on MTD_NAND && SUPERH && CPU_SUBTYPE_SH7723
+ help
+ Several Renesas SuperH CPU has FLCTL. This option enables support
+ for NAND Flash using FLCTL. This driver support SH7723.
+
endif # MTD_NAND
obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
+obj-$(CONFIG_MTD_NAND_TOTO) += toto.o
obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
obj-$(CONFIG_MTD_NAND_EDB7312) += edb7312.o
obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
+ obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
+obj-$(CONFIG_MTD_NAND_OMAP) += omap-nand-flash.o
+obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o
+obj-$(CONFIG_MTD_NAND_OMAP_HW) += omap-hw.o
obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
+ obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o
+ obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
nand-objs := nand_base.o nand_bbt.o
*
* OneNAND driver for OMAP2 / OMAP3
*
- * Copyright (C) 2005-2006 Nokia Corporation
+ * Copyright © 2005-2006 Nokia Corporation
*
- * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
+ * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
* IRQ and DMA support written by Timo Teras
*
* This program is free software; you can redistribute it and/or modify it
#include <asm/io.h>
#include <asm/mach/flash.h>
-#include <asm/arch/gpmc.h>
-#include <asm/arch/onenand.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/gpmc.h>
-#include <asm/arch/pm.h>
+#include <mach/gpmc.h>
+#include <mach/onenand.h>
+#include <mach/gpio.h>
+#include <mach/pm.h>
#include <linux/dma-mapping.h>
#include <asm/dma-mapping.h>
-#include <asm/arch/dma.h>
+#include <mach/dma.h>
-#include <asm/arch/board.h>
+#include <mach/board.h>
#define DRIVER_NAME "omap2-onenand"
}
}
} else {
+ int retry_cnt = 0;
+
/* Turn interrupts off */
syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
syscfg &= ~ONENAND_SYS_CFG1_IOBE;
write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
timeout = jiffies + msecs_to_jiffies(20);
- while (time_before(jiffies, timeout)) {
- intr = read_reg(c, ONENAND_REG_INTERRUPT);
- if (intr & ONENAND_INT_MASTER)
+ while (1) {
+ if (time_before(jiffies, timeout)) {
+ intr = read_reg(c, ONENAND_REG_INTERRUPT);
+ if (intr & ONENAND_INT_MASTER)
+ break;
+ } else {
+ /* Timeout after 20ms */
+ ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
+ if (ctrl & ONENAND_CTRL_ONGO) {
+ /*
+ * The operation seems to be still going
+ * so give it some more time.
+ */
+ retry_cnt += 1;
+ if (retry_cnt < 3) {
+ timeout = jiffies +
+ msecs_to_jiffies(20);
+ continue;
+ }
+ }
break;
+ }
}
}
#define SMC_USE_16BIT 0
#define SMC_USE_32BIT 1
#define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
+#elif defined(CONFIG_ARCH_OMAP34XX)
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
+ #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
+ #define SMC_MEM_RESERVED 1
+#elif defined(CONFIG_ARCH_OMAP24XX)
+ #define SMC_USE_16BIT 0
+ #define SMC_USE_32BIT 1
+ #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
+ #define SMC_MEM_RESERVED 1
#else
/*
* Default configuration
#define SMC_DYNAMIC_BUS_CONFIG
#endif
+ #ifdef SMC_USE_PXA_DMA
+ #define SMC_USE_DMA
+ #endif
+
/* store this information for the driver.. */
struct smc911x_local {
/*
#ifdef SMC_USE_PXA_DMA
- #define SMC_USE_DMA
-
/*
* Define the request and free functions
* These are unfortunately architecture specific as no generic allocation
#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
/* Chip ID values */
- #define CHIP_9115 0x115
- #define CHIP_9116 0x116
- #define CHIP_9117 0x117
- #define CHIP_9118 0x118
+ #define CHIP_9115 0x0115
+ #define CHIP_9116 0x0116
+ #define CHIP_9117 0x0117
+ #define CHIP_9118 0x0118
+ #define CHIP_9215 0x115A
+ #define CHIP_9217 0x117A
+ #define CHIP_9218 0x118A
struct chip_id {
u16 id;
{ CHIP_9116, "LAN9116" },
{ CHIP_9117, "LAN9117" },
{ CHIP_9118, "LAN9118" },
+ { CHIP_9215, "LAN9215" },
+ { CHIP_9217, "LAN9217" },
+ { CHIP_9218, "LAN9218" },
{ 0, NULL },
};
unsigned int ctl, cfg;
struct sk_buff *pending_skb;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
/* Disable all interrupts, block TX tasklet */
spin_lock_irq(&lp->lock);
void __iomem *ioaddr = lp->base;
int mask;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
/* see the header file for options in TCR/RCR DEFAULT */
SMC_SELECT_BANK(lp, 0);
void __iomem *ioaddr = lp->base;
struct sk_buff *pending_skb;
- DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
+ DBG(2, "%s: %s\n", CARDNAME, __func__);
/* no more interrupts for me */
spin_lock_irq(&lp->lock);
void __iomem *ioaddr = lp->base;
unsigned int packet_number, status, packet_len;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
packet_number = SMC_GET_RXFIFO(lp);
if (unlikely(packet_number & RXFIFO_REMPTY)) {
dev->name, packet_number, status,
packet_len, packet_len);
+ if (unlikely(packet_len == 0 && !(status & RS_ERRORS))) {
+ printk(KERN_ERR "%s: bad memory timings: rxlen %u status %x\n",
+ dev->name, packet_len, status);
+ status |= RS_TOOSHORT;
+ }
back:
if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
unsigned int packet_no, len;
unsigned char *buf;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
if (!smc_special_trylock(&lp->lock)) {
netif_stop_queue(dev);
void __iomem *ioaddr = lp->base;
unsigned int numPages, poll_count, status;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
BUG_ON(lp->pending_tx_skb != NULL);
void __iomem *ioaddr = lp->base;
unsigned int saved_packet, packet_no, tx_status, pkt_len;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
/* If the TX FIFO is empty then nothing to do */
packet_no = SMC_GET_TXFIFO(lp);
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
- __FUNCTION__, phyaddr, phyreg, phydata);
+ __func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
return phydata;
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
- __FUNCTION__, phyaddr, phyreg, phydata);
+ __func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
}
struct smc_local *lp = netdev_priv(dev);
int phyaddr;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
lp->phy_type = 0;
int phyaddr = lp->mii.phy_id;
int bmcr, cfg1;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
/* Enter Link Disable state */
cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
int phyaddr = lp->mii.phy_id;
int phy18;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
if (lp->phy_type == 0)
return;
int status, mask, timeout, card_stats;
int saved_pointer;
- DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(3, "%s: %s\n", dev->name, __func__);
spin_lock(&lp->lock);
void __iomem *ioaddr = lp->base;
int status, mask, eph_st, meminfo, fifo;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
spin_lock_irq(&lp->lock);
status = SMC_GET_INT(lp);
unsigned char multicast_table[8];
int update_multicast = 0;
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
if (dev->flags & IFF_PROMISC) {
DBG(2, "%s: RCR_PRMS\n", dev->name);
{
struct smc_local *lp = netdev_priv(dev);
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
/*
* Check that the address is valid. If its not, refuse
* address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
*/
if (!is_valid_ether_addr(dev->dev_addr)) {
- PRINTK("%s: no valid ethernet hw addr\n", __FUNCTION__);
+ PRINTK("%s: no valid ethernet hw addr\n", __func__);
return -EINVAL;
}
/* Setup the default Register Modes */
lp->tcr_cur_mode = TCR_DEFAULT;
lp->rcr_cur_mode = RCR_DEFAULT;
- lp->rpc_cur_mode = RPC_DEFAULT;
+ lp->rpc_cur_mode = RPC_DEFAULT |
+ lp->cfg.leda << RPC_LSXA_SHFT |
+ lp->cfg.ledb << RPC_LSXB_SHFT;
/*
* If we are not using a MII interface, we need to
{
struct smc_local *lp = netdev_priv(dev);
- DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
+ DBG(2, "%s: %s\n", dev->name, __func__);
netif_stop_queue(dev);
netif_carrier_off(dev);
int timeout = 20;
unsigned long cookie;
- DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
+ DBG(2, "%s: %s\n", CARDNAME, __func__);
cookie = probe_irq_on();
const char *version_string;
DECLARE_MAC_BUF(mac);
- DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
+ DBG(2, "%s: %s\n", CARDNAME, __func__);
/* First, see if the high byte is 0x33 */
val = SMC_CURRENT_BANK(lp);
if (dev->dma != (unsigned char)-1)
printk(" DMA %d", dev->dma);
- printk("%s%s\n", nowait ? " [nowait]" : "",
+ printk("%s%s\n",
+ lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
if (!is_valid_ether_addr(dev->dev_addr)) {
lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
}
+ if (!lp->cfg.leda && !lp->cfg.ledb) {
+ lp->cfg.leda = RPC_LSA_DEFAULT;
+ lp->cfg.ledb = RPC_LSB_DEFAULT;
+ }
+
ndev->dma = (unsigned char)-1;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
help
Say Y to enable support for the battery on the OLPC laptop.
- config BATTERY_BQ27x00
- tristate "BQ27x00 battery driver"
- help
- Say Y here to enable support for batteries with BQ27000 or BQ27200 chip.
-
- config BATTERY_BQ27000
- bool "BQ27000 battery driver"
- depends on BATTERY_BQ27x00
- select W1
- select W1_SLAVE_BQ27000
- help
- Say Y here to enable support for batteries with BQ27000(HDQ) chip.
-
- config BATTERY_BQ27200
- bool "BQ27200 battery driver"
- depends on BATTERY_BQ27x00
- select I2C
- select I2C_OMAP
+ config BATTERY_TOSA
+ tristate "Sharp SL-6000 (tosa) battery"
+ depends on MACH_TOSA && MFD_TC6393XB && TOUCHSCREEN_WM97XX
help
- Say Y here to enable support for batteries with BQ27200(I2C) chip.
+ Say Y to enable support for the battery on the Sharp Zaurus
+ SL-6000 (tosa) models.
- config BATTERY_TOSA
- tristate "Sharp SL-6000 (tosa) battery"
- depends on MACH_TOSA && MFD_TC6393XB
+config TWL4030_BCI_BATTERY
+ tristate "OMAP TWL4030 BCI Battery driver"
+ depends on (MACH_OMAP_2430SDP || MACH_OMAP_3430SDP || MACH_OMAP_LDP) && TWL4030_MADC
+ default y
+ help
+ Support for OMAP TWL4030 BCI Battery driver.
+ This driver can give support for TWL4030 Battery Charge Interface.
+
+ config BATTERY_WM97XX
+ bool "WM97xx generic battery driver"
+ depends on TOUCHSCREEN_WM97XX=y
help
- Say Y to enable support for the battery on the Sharp Zaurus
- SL-6000 (tosa) models.
+ Say Y to enable support for battery measured by WM97xx aux port.
- config BATTERY_PALMTX
- tristate "Palm T|X battery"
- depends on MACH_PALMTX
+ config BATTERY_BQ27x00
+ tristate "BQ27200 battery driver"
+ depends on I2C
help
- Say Y to enable support for the battery in Palm T|X.
+ Say Y here to enable support for batteries with BQ27200(I2C) chip.
endif # POWER_SUPPLY
obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o
obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o
obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o
+obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o
+obj-$(CONFIG_TWL4030_BCI_BATTERY) += twl4030_bci_battery.o
obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o
- obj-$(CONFIG_BATTERY_PALMTX) += palmtx_battery.o
+ obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o
+ obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o
#include "8250.h"
+ #ifdef CONFIG_SPARC
+ #include "suncore.h"
+ #endif
+
/*
* Configuration:
* share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
+ static struct uart_driver serial8250_reg;
+
+ static int serial_index(struct uart_port *port)
+ {
+ return (serial8250_reg.minor - 64) + port->line;
+ }
+
/*
* Debugging.
*/
};
struct irq_info {
- spinlock_t lock;
+ struct hlist_node node;
+ int irq;
+ spinlock_t lock; /* Protects list not the hash */
struct list_head *head;
};
- static struct irq_info irq_lists[NR_IRQS];
+ #define NR_IRQ_HASH 32 /* Can be adjusted later */
+ static struct hlist_head irq_lists[NR_IRQ_HASH];
+ static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
/*
* Here we define the default xmit fifo size used for each type of UART.
/*
* FIFO support.
*/
- static inline void serial8250_clear_fifos(struct uart_8250_port *p)
+ static void serial8250_clear_fifos(struct uart_8250_port *p)
{
if (p->capabilities & UART_CAP_FIFO) {
serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
* capability" bit enabled. Note that on XR16C850s, we need to
* reset LCR to write to IER.
*/
- static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
+ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
{
if (p->capabilities & UART_CAP_SLEEP) {
if (p->capabilities & UART_CAP_EFR) {
return;
DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
- up->port.line, up->port.iobase, up->port.membase);
+ serial_index(&up->port), up->port.iobase, up->port.membase);
/*
* We really do need global IRQs disabled here - we're going to
if (up->capabilities != uart_config[up->port.type].flags) {
printk(KERN_WARNING
"ttyS%d: detected caps %08x should be %08x\n",
- up->port.line, up->capabilities,
- uart_config[up->port.type].flags);
+ serial_index(&up->port), up->capabilities,
+ uart_config[up->port.type].flags);
}
up->port.fifosize = uart_config[up->port.type].fifo_size;
/*
* This handles the interrupt from one port.
*/
- static inline void
- serial8250_handle_port(struct uart_8250_port *up)
+ static void serial8250_handle_port(struct uart_8250_port *up)
{
unsigned int status;
unsigned long flags;
DEBUG_INTR("end.\n");
+#ifdef CONFIG_ARCH_OMAP15XX
+ return IRQ_HANDLED; /* FIXME: iir status not ready on 1510 */
+#else
return IRQ_RETVAL(handled);
+#endif
}
/*
BUG_ON(i->head != &up->list);
i->head = NULL;
}
-
spin_unlock_irq(&i->lock);
+ /* List empty so throw away the hash node */
+ if (i->head == NULL) {
+ hlist_del(&i->node);
+ kfree(i);
+ }
}
static int serial_link_irq_chain(struct uart_8250_port *up)
{
- struct irq_info *i = irq_lists + up->port.irq;
+ struct hlist_head *h;
+ struct hlist_node *n;
+ struct irq_info *i;
int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
+ mutex_lock(&hash_mutex);
+
+ h = &irq_lists[up->port.irq % NR_IRQ_HASH];
+
+ hlist_for_each(n, h) {
+ i = hlist_entry(n, struct irq_info, node);
+ if (i->irq == up->port.irq)
+ break;
+ }
+
+ if (n == NULL) {
+ i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
+ if (i == NULL) {
+ mutex_unlock(&hash_mutex);
+ return -ENOMEM;
+ }
+ spin_lock_init(&i->lock);
+ i->irq = up->port.irq;
+ hlist_add_head(&i->node, h);
+ }
+ mutex_unlock(&hash_mutex);
+
spin_lock_irq(&i->lock);
if (i->head) {
static void serial_unlink_irq_chain(struct uart_8250_port *up)
{
- struct irq_info *i = irq_lists + up->port.irq;
+ struct irq_info *i;
+ struct hlist_node *n;
+ struct hlist_head *h;
+ mutex_lock(&hash_mutex);
+
+ h = &irq_lists[up->port.irq % NR_IRQ_HASH];
+
+ hlist_for_each(n, h) {
+ i = hlist_entry(n, struct irq_info, node);
+ if (i->irq == up->port.irq)
+ break;
+ }
+
+ BUG_ON(n == NULL);
BUG_ON(i->head == NULL);
if (list_empty(i->head))
free_irq(up->port.irq, i);
serial_do_unlink(i, up);
+ mutex_unlock(&hash_mutex);
}
/* Base timer interval for polling */
/*
* Wait for transmitter & holding register to empty
*/
- static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
+ static void wait_for_xmitr(struct uart_8250_port *up, int bits)
{
unsigned int status, tmout = 10000;
*/
if (!(up->port.flags & UPF_BUGGY_UART) &&
(serial_inp(up, UART_LSR) == 0xff)) {
- printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
+ printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
+ serial_index(&up->port));
return -ENODEV;
}
*/
if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
up->bugs |= UART_BUG_THRE;
- pr_debug("ttyS%d - using backup timer\n", port->line);
+ pr_debug("ttyS%d - using backup timer\n",
+ serial_index(port));
}
}
if (!(up->bugs & UART_BUG_TXEN)) {
up->bugs |= UART_BUG_TXEN;
pr_debug("ttyS%d - enabling bad tx status workarounds\n",
- port->line);
+ serial_index(port));
}
} else {
up->bugs &= ~UART_BUG_TXEN;
/* emulated UARTs (Lucent Venus 167x) need two steps */
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
}
+
+ /* Note that we need to set ECB to access write water mark
+ * bits. First allow FCR tx fifo write, then set fcr with
+ * possible TX fifo settings. */
+ if (uart_config[up->port.type].flags & UART_CAP_EFR) {
+ serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
+ serial_outp(up, UART_EFR, UART_EFR_ECB);
+ serial_outp(up, UART_LCR, 0x0); /* Access FCR */
+ serial_outp(up, UART_FCR, fcr);
+ serial_outp(up, UART_LCR, 0xbf); /* Access EFR */
+ serial_outp(up, UART_EFR, 0);
+ serial_outp(up, UART_LCR, cval); /* Access FCR */
+ } else
serial_outp(up, UART_FCR, fcr); /* set fcr */
}
serial8250_set_mctrl(&up->port, up->port.mctrl);
static int
serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
{
- if (ser->irq >= NR_IRQS || ser->irq < 0 ||
+ if (ser->irq >= nr_irqs || ser->irq < 0 ||
ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
ser->type == PORT_STARTECH)
return serial8250_find_port_for_earlycon();
}
- static struct uart_driver serial8250_reg;
static struct console serial8250_console = {
.name = "ttyS",
.write = serial8250_console_write,
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
- .nr = UART_NR,
.cons = SERIAL8250_CONSOLE,
};
static int __init serial8250_init(void)
{
- int ret, i;
+ int ret;
if (nr_uarts > UART_NR)
nr_uarts = UART_NR;
"%d ports, IRQ sharing %sabled\n", nr_uarts,
share_irqs ? "en" : "dis");
- for (i = 0; i < NR_IRQS; i++)
- spin_lock_init(&irq_lists[i].lock);
-
+ #ifdef CONFIG_SPARC
+ ret = sunserial_register_minors(&serial8250_reg, UART_NR);
+ #else
+ serial8250_reg.nr = UART_NR;
ret = uart_register_driver(&serial8250_reg);
+ #endif
if (ret)
goto out;
goto out;
platform_device_del(serial8250_isa_devs);
- put_dev:
+ put_dev:
platform_device_put(serial8250_isa_devs);
- unreg_uart_drv:
+ unreg_uart_drv:
+ #ifdef CONFIG_SPARC
+ sunserial_unregister_minors(&serial8250_reg, UART_NR);
+ #else
uart_unregister_driver(&serial8250_reg);
- out:
+ #endif
+ out:
return ret;
}
platform_driver_unregister(&serial8250_isa_driver);
platform_device_unregister(isa_dev);
+ #ifdef CONFIG_SPARC
+ sunserial_unregister_minors(&serial8250_reg, UART_NR);
+ #else
uart_unregister_driver(&serial8250_reg);
+ #endif
}
module_init(serial8250_init);
default y if PXA3xx
default y if ARCH_EP93XX
default y if ARCH_AT91
- default y if ARCH_PNX4008
+ default y if ARCH_PNX4008 && I2C
+ default y if MFD_TC6393XB
# PPC:
default y if STB03xxx
default y if PPC_MPC52xx
default y if PPC_83xx
default y if SOC_AU1200
default y if ARCH_IXP4XX
+ default y if ARCH_OMAP34XX
default PCI
# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
source "drivers/usb/mon/Kconfig"
+ source "drivers/usb/wusbcore/Kconfig"
+
source "drivers/usb/host/Kconfig"
source "drivers/usb/musb/Kconfig"
To compile this driver as a module, choose M here: the
module will be called ehci-hcd.
+choice
+ prompt "PHY/TLL mode"
+ depends on USB_EHCI_HCD && EXPERIMENTAL && ARCH_OMAP34XX
+ ---help---
+ Choose PHY or TLL mode of operation
+
+config OMAP_EHCI_PHY_MODE
+ bool "PHY mode: ISP1504 on Port1/2 (NEW 3430ES2.0)"
+ depends on USB_EHCI_HCD && EXPERIMENTAL && ARCH_OMAP34XX
+ ---help---
+ EHCI PHY mode. Port1 and Port2 are connected to ISP1504 transcievers
+
+config OMAP_EHCI_TLL_MODE
+ bool "TLL mode: (EXPERIMENTAL)"
+ depends on USB_EHCI_HCD && EXPERIMENTAL && ARCH_OMAP34XX
+ ---help---
+ OMAP EHCI controller has TLL mode of operation for all 3 ports.
+ Use this mode when no transciever is present
+endchoice
config USB_EHCI_ROOT_HUB_TT
bool "Root Hub Transaction Translators"
tristate "OHCI HCD support"
depends on USB && USB_ARCH_HAS_OHCI
select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
- select I2C if ARCH_PNX4008
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
help
This driver enables support for the on-chip R8A66597 in the
SH7366 and SH7723 processors.
+
+ config USB_WHCI_HCD
+ tristate "Wireless USB Host Controller Interface (WHCI) driver (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ depends on PCI && USB
+ select USB_WUSB
+ select UWB_WHCI
+ help
+ A driver for PCI-based Wireless USB Host Controllers that are
+ compliant with the WHCI specification.
+
+ To compile this driver a module, choose M here: the module
+ will be called "whci-hcd".
+
+ config USB_HWA_HCD
+ tristate "Host Wire Adapter (HWA) driver (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ depends on USB
+ select USB_WUSB
+ select UWB_HWA
+ help
+ This driver enables you to connect Wireless USB devices to
+ your system using a Host Wire Adaptor USB dongle. This is an
+ UWB Radio Controller and WUSB Host Controller connected to
+ your machine via USB (specified in WUSB1.0).
+
+ To compile this driver a module, choose M here: the module
+ will be called "hwa-hc".
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
+ #include <linux/vmalloc.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/timer.h>
* providing early devices for those host controllers to talk to!
*/
- #define DRIVER_VERSION "10 Dec 2004"
#define DRIVER_AUTHOR "David Brownell"
#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci_info (ehci,
- "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
+ "USB %x.%x started, EHCI %x.%02x%s\n",
((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
- temp >> 8, temp & 0xff, DRIVER_VERSION,
+ temp >> 8, temp & 0xff,
ignore_oc ? ", overcurrent ignored" : "");
ehci_writel(ehci, INTR_MASK,
pcd_status = status;
/* resume root hub? */
- if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN))
+ if (!(cmd & CMD_RUN))
usb_hcd_resume_root_hub(hcd);
while (i--) {
if (pstatus & PORT_OWNER)
continue;
- if (!(pstatus & PORT_RESUME)
- || ehci->reset_done [i] != 0)
+ if (!(test_bit(i, &ehci->suspended_ports) &&
+ ((pstatus & PORT_RESUME) ||
+ !(pstatus & PORT_SUSPEND)) &&
+ (pstatus & PORT_PE) &&
+ ehci->reset_done[i] == 0))
continue;
/* start 20 msec resume signaling from this port,
/* PCI errors [4.15.2.4] */
if (unlikely ((status & STS_FATAL) != 0)) {
- dbg_cmd (ehci, "fatal", ehci_readl(ehci,
- &ehci->regs->command));
- dbg_status (ehci, "fatal", status);
+ dbg_cmd(ehci, "fatal", cmd);
+ dbg_status(ehci, "fatal", status);
if (status & STS_HALT) {
ehci_err (ehci, "fatal error\n");
dead:
/*-------------------------------------------------------------------------*/
- #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
-
- MODULE_DESCRIPTION (DRIVER_INFO);
+ MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR (DRIVER_AUTHOR);
MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
#endif
+#ifdef CONFIG_ARCH_OMAP34XX
+#include "ehci-omap.c"
+#define PLATFORM_DRIVER ehci_hcd_omap_driver
+#endif
+
#ifdef CONFIG_PPC_PS3
#include "ehci-ps3.c"
#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
#endif
- #if defined(CONFIG_440EPX) && !defined(CONFIG_PPC_MERGE)
- #include "ehci-ppc-soc.c"
- #define PLATFORM_DRIVER ehci_ppc_soc_driver
- #endif
-
#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
#include "ehci-ppc-of.c"
#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
{
int retval = 0;
+ if (usb_disabled())
+ return -ENODEV;
+
+ printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
+ set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
+ if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
+ test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
+ printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
+ " before uhci_hcd and ohci_hcd, not after\n");
+
pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
hcd_name,
sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
#ifdef DEBUG
ehci_debug_root = debugfs_create_dir("ehci", NULL);
- if (!ehci_debug_root)
- return -ENOENT;
+ if (!ehci_debug_root) {
+ retval = -ENOENT;
+ goto err_debug;
+ }
#endif
#ifdef PLATFORM_DRIVER
#ifdef DEBUG
debugfs_remove(ehci_debug_root);
ehci_debug_root = NULL;
+ err_debug:
#endif
+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
return retval;
}
module_init(ehci_hcd_init);
#ifdef DEBUG
debugfs_remove(ehci_debug_root);
#endif
+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
}
module_exit(ehci_hcd_cleanup);
extern void omap_dispc_enable_lcd_out(int enable);
extern void omap_dispc_enable_digit_out(int enable);
-extern int omap_dispc_request_irq(void (*callback)(void *data), void *data);
-extern void omap_dispc_free_irq(void);
+extern int omap_dispc_request_irq(unsigned long irq_mask,
+ void (*callback)(void *data), void *data);
+extern void omap_dispc_free_irq(unsigned long irq_mask,
+ void (*callback)(void *data), void *data);
extern const struct lcd_ctrl omap2_int_ctrl;
+
#endif
#include "w1_family.h"
#define W1_MAXNAMELEN 32
- #define W1_SLAVE_DATA_SIZE 128
#define W1_SEARCH 0xF0
#define W1_ALARM_SEARCH 0xEC
struct completion released;
};
- typedef void (* w1_slave_found_callback)(void *, u64);
+ typedef void (*w1_slave_found_callback)(struct w1_master *, u64);
/**
*/
u8 (*reset_bus)(void *);
- /** Really nice hardware can handles the different types of ROM search */
- void (*search)(void *, u8, w1_slave_found_callback);
- };
+ /**
+ * Put out a strong pull-up pulse of the specified duration.
+ * @return -1=Error, 0=completed
+ */
+ u8 (*set_pullup)(void *, int);
- #define W1_MASTER_NEED_EXIT 0
- #define W1_MASTER_NEED_RECONNECT 1
+ /** Really nice hardware can handles the different types of ROM search
+ * w1_master* is passed to the slave found callback.
+ */
+ void (*search)(void *, struct w1_master *,
+ u8, w1_slave_found_callback);
+ };
struct w1_master
{
void *priv;
int priv_size;
- long flags;
+ /** 5V strong pullup enabled flag, 1 enabled, zero disabled. */
+ int enable_pullup;
+ /** 5V strong pullup duration in milliseconds, zero disabled. */
+ int pullup_duration;
struct task_struct *thread;
struct mutex mutex;
};
int w1_create_master_attributes(struct w1_master *);
+ void w1_destroy_master_attributes(struct w1_master *master);
void w1_search(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb);
void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb);
struct w1_slave *w1_search_slave(struct w1_reg_num *id);
void w1_search_process(struct w1_master *dev, u8 search_type);
struct w1_master *w1_search_master_id(u32 id);
+ /* Disconnect and reconnect devices in the given family. Used for finding
+ * unclaimed devices after a family has been registered or releasing devices
+ * after a family has been unregistered. Set attach to 1 when a new family
+ * has just been registered, to 0 when it has been unregistered.
+ */
+ void w1_reconnect_slaves(struct w1_family *f, int attach);
+ void w1_slave_detach(struct w1_slave *sl);
+
u8 w1_triplet(struct w1_master *dev, int bdir);
void w1_write_8(struct w1_master *, u8);
+u8 w1_read_8(struct w1_master *);
int w1_reset_bus(struct w1_master *);
u8 w1_calc_crc8(u8 *, int);
void w1_write_block(struct w1_master *, const u8 *, int);
u8 w1_read_block(struct w1_master *, u8 *, int);
int w1_reset_select_slave(struct w1_slave *sl);
+ void w1_next_pullup(struct w1_master *, int);
static inline struct w1_slave* dev_to_w1_slave(struct device *dev)
{
}
}
+ /**
+ * Pre-write operation, currently only supporting strong pullups.
+ * Program the hardware for a strong pullup, if one has been requested and
+ * the hardware supports it.
+ *
+ * @param dev the master device
+ */
+ static void w1_pre_write(struct w1_master *dev)
+ {
+ if (dev->pullup_duration &&
+ dev->enable_pullup && dev->bus_master->set_pullup) {
+ dev->bus_master->set_pullup(dev->bus_master->data,
+ dev->pullup_duration);
+ }
+ }
+
+ /**
+ * Post-write operation, currently only supporting strong pullups.
+ * If a strong pullup was requested, clear it if the hardware supports
+ * them, or execute the delay otherwise, in either case clear the request.
+ *
+ * @param dev the master device
+ */
+ static void w1_post_write(struct w1_master *dev)
+ {
+ if (dev->pullup_duration) {
+ if (dev->enable_pullup && dev->bus_master->set_pullup)
+ dev->bus_master->set_pullup(dev->bus_master->data, 0);
+ else
+ msleep(dev->pullup_duration);
+ dev->pullup_duration = 0;
+ }
+ }
+
/**
* Writes 8 bits.
*
{
int i;
- if (dev->bus_master->write_byte)
+ if (dev->bus_master->write_byte) {
+ w1_pre_write(dev);
dev->bus_master->write_byte(dev->bus_master->data, byte);
+ }
else
- for (i = 0; i < 8; ++i)
+ for (i = 0; i < 8; ++i) {
+ if (i == 7)
+ w1_pre_write(dev);
w1_touch_bit(dev, (byte >> i) & 0x1);
+ }
+ w1_post_write(dev);
}
EXPORT_SYMBOL_GPL(w1_write_8);
* @param dev the master device
* @return the byte read
*/
-static u8 w1_read_8(struct w1_master * dev)
+u8 w1_read_8(struct w1_master *dev)
{
int i;
u8 res = 0;
return res;
}
+EXPORT_SYMBOL_GPL(w1_read_8);
/**
* Writes a series of bytes.
{
int i;
- if (dev->bus_master->write_block)
+ if (dev->bus_master->write_block) {
+ w1_pre_write(dev);
dev->bus_master->write_block(dev->bus_master->data, buf, len);
+ }
else
for (i = 0; i < len; ++i)
- w1_write_8(dev, buf[i]);
+ w1_write_8(dev, buf[i]); /* calls w1_pre_write */
+ w1_post_write(dev);
}
EXPORT_SYMBOL_GPL(w1_write_block);
result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
else {
dev->bus_master->write_bit(dev->bus_master->data, 0);
+ /* minimum 480, max ? us
+ * be nice and sleep, except 18b20 spec lists 960us maximum,
+ * so until we can sleep with microsecond accuracy, spin.
+ * Feel free to come up with some other way to give up the
+ * cpu for such a short amount of time AND get it back in
+ * the maximum amount of time.
+ */
w1_delay(480);
dev->bus_master->write_bit(dev->bus_master->data, 1);
w1_delay(70);
result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
- w1_delay(410);
+ /* minmum 70 (above) + 410 = 480 us
+ * There aren't any timing requirements between a reset and
+ * the following transactions. Sleeping is safe here.
+ */
+ /* w1_delay(410); min required time */
+ msleep(1);
}
return result;
{
dev->attempts++;
if (dev->bus_master->search)
- dev->bus_master->search(dev->bus_master->data, search_type, cb);
+ dev->bus_master->search(dev->bus_master->data, dev,
+ search_type, cb);
else
w1_search(dev, search_type, cb);
}
return 0;
}
EXPORT_SYMBOL_GPL(w1_reset_select_slave);
+
+ /**
+ * Put out a strong pull-up of the specified duration after the next write
+ * operation. Not all hardware supports strong pullups. Hardware that
+ * doesn't support strong pullups will sleep for the given time after the
+ * write operation without a strong pullup. This is a one shot request for
+ * the next write, specifying zero will clear a previous request.
+ * The w1 master lock must be held.
+ *
+ * @param delay time in milliseconds
+ * @return 0=success, anything else=error
+ */
+ void w1_next_pullup(struct w1_master *dev, int delay)
+ {
+ dev->pullup_duration = delay;
+ }
+ EXPORT_SYMBOL_GPL(w1_next_pullup);
Watchdog timer embedded into AT91RM9200 chips. This will reboot your
system when the timeout is reached.
+ config AT91SAM9X_WATCHDOG
+ tristate "AT91SAM9X watchdog"
+ depends on WATCHDOG && (ARCH_AT91SAM9260 || ARCH_AT91SAM9261)
+ help
+ Watchdog timer embedded into AT91SAM9X chips. This will reboot your
+ system when the timeout is reached.
+
config 21285_WATCHDOG
tristate "DC21285 watchdog"
depends on FOOTBRIDGE
config OMAP_WATCHDOG
tristate "OMAP Watchdog"
- depends on ARCH_OMAP16XX || ARCH_OMAP24XX
+ depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
- Support for TI OMAP1610/OMAP1710/OMAP2420 watchdog. Say 'Y' here to
- enable the OMAP1610/OMAP1710 watchdog timer.
+ Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog. Say 'Y'
+ here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430 watchdog timer.
config PNX4008_WATCHDOG
tristate "PNX4008 Watchdog"
NOTE: once enabled, this timer cannot be disabled.
Say N if you are unsure.
+ config ORION5X_WATCHDOG
+ tristate "Orion5x watchdog"
+ depends on ARCH_ORION5X
+ help
+ Say Y here if to include support for the watchdog timer
+ in the Orion5x ARM SoCs.
+ To compile this driver as a module, choose M here: the
+ module will be called orion5x_wdt.
+
# ARM26 Architecture
# AVR32 Architecture
To compile this driver as a module, choose M here: the
module will be called it8712f_wdt.
+ config IT87_WDT
+ tristate "IT87 Watchdog Timer"
+ depends on X86 && EXPERIMENTAL
+ ---help---
+ This is the driver for the hardware watchdog on the ITE IT8716,
+ IT8718, IT8726, IT8712(Version J,K) Super I/O chips. This watchdog
+ simply watches your kernel to make sure it doesn't freeze, and if
+ it does, it reboots your computer after a certain amount of time.
+
+ To compile this driver as a module, choose M here: the module will
+ be called it87_wdt.
+
config HP_WATCHDOG
tristate "HP Proliant iLO 2 Hardware Watchdog Timer"
depends on X86
Most people will say N.
+ config W83697UG_WDT
+ tristate "W83697UG/W83697UF Watchdog Timer"
+ depends on X86
+ ---help---
+ This is the driver for the hardware watchdog on the W83697UG/UF
+ chipset as used in MSI Fuzzy CX700 VIA motherboards (and likely others).
+ This watchdog simply watches your kernel to make sure it doesn't
+ freeze, and if it does, it reboots your computer after a certain
+ amount of time.
+
+ To compile this driver as a module, choose M here: the
+ module will be called w83697ug_wdt.
+
+ Most people will say N.
+
config W83877F_WDT
tristate "W83877F (EMACS) Watchdog Timer"
depends on X86
#define I2C_DRIVERID_MSP3400 1
#define I2C_DRIVERID_TUNER 2
+#define I2C_DRIVERID_TDA8425 4 /* stereo sound processor */
#define I2C_DRIVERID_TEA6420 5 /* audio matrix switch */
#define I2C_DRIVERID_TEA6415C 6 /* video matrix switch */
#define I2C_DRIVERID_TDA9840 7 /* stereo sound processor */
#define I2C_DRIVERID_SAA7111A 8 /* video input processor */
#define I2C_DRIVERID_SAA7185B 13 /* video encoder */
+#define I2C_DRIVERID_TEA6300 18 /* audio mixer */
+#define I2C_DRIVERID_TDA9850 20 /* audio mixer */
+#define I2C_DRIVERID_TDA9855 21 /* audio mixer */
#define I2C_DRIVERID_SAA7110 22 /* video decoder */
#define I2C_DRIVERID_SAA5249 24 /* SAA5249 and compatibles */
#define I2C_DRIVERID_PCF8583 25 /* real time clock */
- #define I2C_DRIVERID_SAB3036 26 /* SAB3036 tuner */
#define I2C_DRIVERID_TDA7432 27 /* Stereo sound processor */
#define I2C_DRIVERID_TVMIXER 28 /* Mixer driver for tv cards */
#define I2C_DRIVERID_TVAUDIO 29 /* Generic TV sound driver */
+#define I2C_DRIVERID_TDA9873 31 /* TV sound decoder chip */
#define I2C_DRIVERID_TDA9875 32 /* TV sound decoder chip */
+#define I2C_DRIVERID_PIC16C54_PV9 33 /* Audio mux/ir receiver */
#define I2C_DRIVERID_BT819 40 /* video decoder */
#define I2C_DRIVERID_BT856 41 /* video encoder */
#define I2C_DRIVERID_VPX3220 42 /* video decoder+vbi/vtxt */
#define I2C_DRIVERID_INDYCAM 58 /* SGI IndyCam */
#define I2C_DRIVERID_OVCAMCHIP 61 /* OmniVision CMOS image sens. */
#define I2C_DRIVERID_MAX6900 63 /* MAX6900 real-time clock */
+#define I2C_DRIVERID_TDA9874 66 /* TV sound decoder */
#define I2C_DRIVERID_SAA6752HS 67 /* MPEG2 encoder */
#define I2C_DRIVERID_TVEEPROM 68 /* TV EEPROM */
#define I2C_DRIVERID_WM8775 69 /* wm8775 audio processor */
#define I2C_DRIVERID_CS53L32A 70 /* cs53l32a audio processor */
#define I2C_DRIVERID_CX25840 71 /* cx2584x video encoder */
- #define I2C_DRIVERID_SAA7127 72 /* saa7124 video encoder */
+ #define I2C_DRIVERID_SAA7127 72 /* saa7127 video encoder */
#define I2C_DRIVERID_SAA711X 73 /* saa711x video encoders */
#define I2C_DRIVERID_AKITAIOEXP 74 /* IO Expander on Sharp SL-C1000 */
#define I2C_DRIVERID_INFRARED 75 /* I2C InfraRed on Video boards */
#define I2C_DRIVERID_M52790 95 /* Mitsubishi M52790SP/FP AV switch */
#define I2C_DRIVERID_CS5345 96 /* cs5345 audio processor */
+#define I2C_DRIVERID_MISC 99 /* Whatever until sorted out */
+
+#define I2C_DRIVERID_I2CDEV 900
+
#define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */
/*
#define I2C_HW_B_RIVA 0x010010 /* Riva based graphics cards */
#define I2C_HW_B_IOC 0x010011 /* IOC bit-wiggling */
#define I2C_HW_B_IXP2000 0x010016 /* GPIO on IXP2000 systems */
+#define I2C_HW_B_S3VIA 0x010018 /* S3Via ProSavage adapter */
#define I2C_HW_B_ZR36067 0x010019 /* Zoran-36057/36067 based boards */
#define I2C_HW_B_PCILYNX 0x01001a /* TI PCILynx I2C adapter */
#define I2C_HW_B_CX2388x 0x01001b /* connexant 2388x based tv cards */
#define I2C_HW_SMBUS_W9968CF 0x04000d
#define I2C_HW_SMBUS_OV511 0x04000e /* OV511(+) USB 1.1 webcam ICs */
#define I2C_HW_SMBUS_OV518 0x04000f /* OV518(+) USB 1.1 webcam ICs */
+#define I2C_HW_SMBUS_OVFX2 0x040011 /* Cypress/OmniVision FX2 webcam */
#define I2C_HW_SMBUS_CAFE 0x040012 /* Marvell 88ALP01 "CAFE" cam */
#define I2C_HW_SMBUS_ALI1563 0x040013
u16 debounce_tol; /* tolerance used for filtering */
u16 debounce_rep; /* additional consecutive good readings
* required after the first two */
+ int gpio_pendown; /* the GPIO used to decide the pendown
+ * state if get_pendown_state == NULL
+ */
int (*get_pendown_state)(void);
int (*filter_init) (struct ads7846_platform_data *pdata,
void **filter_data);
int (*filter) (void *filter_data, int data_idx, int *val);
void (*filter_cleanup)(void *filter_data);
+
+ /* controls enabling/disabling*/
+ int (*vaux_control)(int vaux_cntrl);
+#define VAUX_ENABLE 1
+#define VAUX_DISABLE 0
};
* Fixed SMP synchronization, 08/08/99, Manfred Spraul
* manfred@colorfullife.com
* Rewrote bits to get rid of console_lock
- * 01Mar01 Andrew Morton <andrewm@uow.edu.au>
+ * 01Mar01 Andrew Morton
*/
#include <linux/kernel.h>
#define __LOG_BUF_LEN (1 << CONFIG_LOG_BUF_SHIFT)
+#ifdef CONFIG_DEBUG_LL
+extern void printascii(char *);
+#endif
+
/* printk's without a loglevel use this.. */
#define DEFAULT_MESSAGE_LOGLEVEL 4 /* KERN_WARNING */
* @fmt: format string
*
* This is printk(). It can be called from any context. We want it to work.
- * Be aware of the fact that if oops_in_progress is not set, we might try to
- * wake klogd up which could deadlock on runqueue lock if printk() is called
- * from scheduler code.
*
* We try to grab the console_sem. If we succeed, it's easy - we log the output and
* call the console drivers. If we fail to get the semaphore we place the output
*
* See also:
* printf(3)
+ *
+ * See the vsnprintf() documentation for format string extensions over C99.
*/
asmlinkage int printk(const char *fmt, ...)
printed_len += vscnprintf(printk_buf + printed_len,
sizeof(printk_buf) - printed_len, fmt, args);
+#ifdef CONFIG_DEBUG_LL
+ printascii(printk_buf);
+#endif
/*
* Copy the output into log_buf. If the caller didn't provide
return console_locked;
}
- void wake_up_klogd(void)
+ static DEFINE_PER_CPU(int, printk_pending);
+
+ void printk_tick(void)
{
- if (!oops_in_progress && waitqueue_active(&log_wait))
+ if (__get_cpu_var(printk_pending)) {
+ __get_cpu_var(printk_pending) = 0;
wake_up_interruptible(&log_wait);
+ }
+ }
+
+ int printk_needs_cpu(int cpu)
+ {
+ return per_cpu(printk_pending, cpu);
+ }
+
+ void wake_up_klogd(void)
+ {
+ if (waitqueue_active(&log_wait))
+ __raw_get_cpu_var(printk_pending) = 1;
}
/**
}
late_initcall(disable_boot_consoles);
- /**
- * tty_write_message - write a message to a certain tty, not just the console.
- * @tty: the destination tty_struct
- * @msg: the message to write
- *
- * This is used for messages that need to be redirected to a specific tty.
- * We don't put it into the syslog queue right now maybe in the future if
- * really needed.
- */
- void tty_write_message(struct tty_struct *tty, char *msg)
- {
- if (tty && tty->ops->write)
- tty->ops->write(tty, msg, strlen(msg));
- return;
- }
-
#if defined CONFIG_PRINTK
/*
menu "IP: Netfilter Configuration"
depends on INET && NETFILTER
+ config NF_DEFRAG_IPV4
+ tristate
+ default n
+
config NF_CONNTRACK_IPV4
tristate "IPv4 connection tracking support (required for NAT)"
depends on NF_CONNTRACK
default m if NETFILTER_ADVANCED=n
+ select NF_DEFRAG_IPV4
---help---
Connection tracking keeps a record of what packets have passed
through your machine, in order to figure out how they are related
To compile it as a module, choose M here. If unsure, say N.
+ if IP_NF_IPTABLES
+
# The matches.
- config IP_NF_MATCH_RECENT
- tristate '"recent" match support'
- depends on IP_NF_IPTABLES
+ config IP_NF_MATCH_ADDRTYPE
+ tristate '"addrtype" address type match support'
depends on NETFILTER_ADVANCED
help
- This match is used for creating one or many lists of recently
- used addresses and then matching against that/those list(s).
+ This option allows you to match what routing thinks of an address,
+ eg. UNICAST, LOCAL, BROADCAST, ...
- Short options are available by using 'iptables -m recent -h'
- Official Website: <http://snowman.net/projects/ipt_recent/>
+ If you want to compile it as a module, say M here and read
+ <file:Documentation/kbuild/modules.txt>. If unsure, say `N'.
+
+ config IP_NF_MATCH_AH
+ tristate '"ah" match support'
+ depends on NETFILTER_ADVANCED
+ help
+ This match extension allows you to match a range of SPIs
+ inside AH header of IPSec packets.
To compile it as a module, choose M here. If unsure, say N.
config IP_NF_MATCH_ECN
tristate '"ecn" match support'
- depends on IP_NF_IPTABLES
depends on NETFILTER_ADVANCED
help
This option adds a `ECN' match, which allows you to match against
To compile it as a module, choose M here. If unsure, say N.
- config IP_NF_MATCH_AH
- tristate '"ah" match support'
- depends on IP_NF_IPTABLES
- depends on NETFILTER_ADVANCED
- help
- This match extension allows you to match a range of SPIs
- inside AH header of IPSec packets.
-
- To compile it as a module, choose M here. If unsure, say N.
-
config IP_NF_MATCH_TTL
tristate '"ttl" match support'
- depends on IP_NF_IPTABLES
depends on NETFILTER_ADVANCED
help
This adds CONFIG_IP_NF_MATCH_TTL option, which enabled the user
To compile it as a module, choose M here. If unsure, say N.
- config IP_NF_MATCH_ADDRTYPE
- tristate '"addrtype" address type match support'
- depends on IP_NF_IPTABLES
- depends on NETFILTER_ADVANCED
- help
- This option allows you to match what routing thinks of an address,
- eg. UNICAST, LOCAL, BROADCAST, ...
-
- If you want to compile it as a module, say M here and read
- <file:Documentation/kbuild/modules.txt>. If unsure, say `N'.
-
# `filter', generic and specific targets
config IP_NF_FILTER
tristate "Packet filtering"
- depends on IP_NF_IPTABLES
default m if NETFILTER_ADVANCED=n
help
Packet filtering defines a table `filter', which has a series of
config IP_NF_TARGET_LOG
tristate "LOG target support"
- depends on IP_NF_IPTABLES
default m if NETFILTER_ADVANCED=n
help
This option adds a `LOG' target, which allows you to create rules in
config IP_NF_TARGET_ULOG
tristate "ULOG target support"
- depends on IP_NF_IPTABLES
default m if NETFILTER_ADVANCED=n
---help---
# NAT + specific targets: nf_conntrack
config NF_NAT
tristate "Full NAT"
- depends on IP_NF_IPTABLES && NF_CONNTRACK_IPV4
+ depends on NF_CONNTRACK_IPV4
default m if NETFILTER_ADVANCED=n
help
The Full NAT option allows masquerading, port forwarding and other
To compile it as a module, choose M here. If unsure, say N.
- config IP_NF_TARGET_REDIRECT
- tristate "REDIRECT target support"
+ config IP_NF_TARGET_NETMAP
+ tristate "NETMAP target support"
depends on NF_NAT
depends on NETFILTER_ADVANCED
help
- REDIRECT is a special case of NAT: all incoming connections are
- mapped onto the incoming interface's address, causing the packets to
- come to the local machine instead of passing through. This is
- useful for transparent proxies.
+ NETMAP is an implementation of static 1:1 NAT mapping of network
+ addresses. It maps the network address part, while keeping the host
+ address part intact.
To compile it as a module, choose M here. If unsure, say N.
- config IP_NF_TARGET_NETMAP
- tristate "NETMAP target support"
+ config IP_NF_TARGET_REDIRECT
+ tristate "REDIRECT target support"
depends on NF_NAT
depends on NETFILTER_ADVANCED
help
- NETMAP is an implementation of static 1:1 NAT mapping of network
- addresses. It maps the network address part, while keeping the host
- address part intact.
+ REDIRECT is a special case of NAT: all incoming connections are
+ mapped onto the incoming interface's address, causing the packets to
+ come to the local machine instead of passing through. This is
+ useful for transparent proxies.
+ To compile it as a module, choose M here. If unsure, say N.
+
+config IP_NF_TARGET_IDLETIMER
+ tristate "IDLETIMER target support"
+ depends on IP_NF_IPTABLES
+ help
+ This option adds a `IDLETIMER' target. Each matching packet resets
+ the timer associated with input and/or output interfaces. Timer
+ expiry causes kobject uevent. Idle timer can be read via sysfs.
+
+ To compile it as a module, choose M here. If unsure, say N.
+
+
To compile it as a module, choose M here. If unsure, say N.
config NF_NAT_SNMP_BASIC
config NF_NAT_FTP
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_FTP
config NF_NAT_IRC
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_IRC
config NF_NAT_TFTP
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_TFTP
config NF_NAT_AMANDA
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_AMANDA
config NF_NAT_PPTP
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_PPTP
select NF_NAT_PROTO_GRE
config NF_NAT_H323
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_H323
config NF_NAT_SIP
tristate
- depends on IP_NF_IPTABLES && NF_CONNTRACK && NF_NAT
+ depends on NF_CONNTRACK && NF_NAT
default NF_NAT && NF_CONNTRACK_SIP
# mangle + specific targets
config IP_NF_MANGLE
tristate "Packet mangling"
- depends on IP_NF_IPTABLES
default m if NETFILTER_ADVANCED=n
help
This option adds a `mangle' table to iptables: see the man page for
To compile it as a module, choose M here. If unsure, say N.
+ config IP_NF_TARGET_CLUSTERIP
+ tristate "CLUSTERIP target support (EXPERIMENTAL)"
+ depends on IP_NF_MANGLE && EXPERIMENTAL
+ depends on NF_CONNTRACK_IPV4
+ depends on NETFILTER_ADVANCED
+ select NF_CONNTRACK_MARK
+ help
+ The CLUSTERIP target allows you to build load-balancing clusters of
+ network servers without having a dedicated load-balancing
+ router/server/switch.
+
+ To compile it as a module, choose M here. If unsure, say N.
+
config IP_NF_TARGET_ECN
tristate "ECN target support"
depends on IP_NF_MANGLE
To compile it as a module, choose M here. If unsure, say N.
- config IP_NF_TARGET_CLUSTERIP
- tristate "CLUSTERIP target support (EXPERIMENTAL)"
- depends on IP_NF_MANGLE && EXPERIMENTAL
- depends on NF_CONNTRACK_IPV4
- depends on NETFILTER_ADVANCED
- select NF_CONNTRACK_MARK
- help
- The CLUSTERIP target allows you to build load-balancing clusters of
- network servers without having a dedicated load-balancing
- router/server/switch.
-
- To compile it as a module, choose M here. If unsure, say N.
-
# raw + specific targets
config IP_NF_RAW
tristate 'raw table support (required for NOTRACK/TRACE)'
- depends on IP_NF_IPTABLES
depends on NETFILTER_ADVANCED
help
This option adds a `raw' table to iptables. This table is the very
# security table for MAC policy
config IP_NF_SECURITY
tristate "Security table"
- depends on IP_NF_IPTABLES
depends on SECURITY
depends on NETFILTER_ADVANCED
help
If unsure, say N.
+ endif # IP_NF_IPTABLES
+
# ARP tables
config IP_NF_ARPTABLES
tristate "ARP tables support"
To compile it as a module, choose M here. If unsure, say N.
+ if IP_NF_ARPTABLES
+
config IP_NF_ARPFILTER
tristate "ARP packet filtering"
- depends on IP_NF_ARPTABLES
help
ARP packet filtering defines a table `filter', which has a series of
rules for simple ARP packet filtering at local input and
config IP_NF_ARP_MANGLE
tristate "ARP payload mangling"
- depends on IP_NF_ARPTABLES
help
Allows altering the ARP packet payload: source and destination
hardware and network addresses.
+ endif # IP_NF_ARPTABLES
+
endmenu
obj-$(CONFIG_NF_NAT) += nf_nat.o
+ # defrag
+ obj-$(CONFIG_NF_DEFRAG_IPV4) += nf_defrag_ipv4.o
+
# NAT helpers (nf_conntrack)
obj-$(CONFIG_NF_NAT_AMANDA) += nf_nat_amanda.o
obj-$(CONFIG_NF_NAT_FTP) += nf_nat_ftp.o
obj-$(CONFIG_IP_NF_MATCH_ADDRTYPE) += ipt_addrtype.o
obj-$(CONFIG_IP_NF_MATCH_AH) += ipt_ah.o
obj-$(CONFIG_IP_NF_MATCH_ECN) += ipt_ecn.o
- obj-$(CONFIG_IP_NF_MATCH_RECENT) += ipt_recent.o
obj-$(CONFIG_IP_NF_MATCH_TTL) += ipt_ttl.o
# targets
obj-$(CONFIG_IP_NF_TARGET_NETMAP) += ipt_NETMAP.o
obj-$(CONFIG_IP_NF_TARGET_REDIRECT) += ipt_REDIRECT.o
obj-$(CONFIG_IP_NF_TARGET_REJECT) += ipt_REJECT.o
+obj-$(CONFIG_IP_NF_TARGET_IDLETIMER) += ipt_IDLETIMER.o
obj-$(CONFIG_IP_NF_TARGET_TTL) += ipt_TTL.o
obj-$(CONFIG_IP_NF_TARGET_ULOG) += ipt_ULOG.o
If you are unsure how to answer this question, answer N.
+ config SECURITYFS
+ bool "Enable the securityfs filesystem"
+ help
+ This will build the securityfs filesystem. It is currently used by
+ the TPM bios character driver. It is not used by SELinux or SMACK.
+
+ If you are unsure how to answer this question, answer N.
+
config SECURITY_NETWORK
bool "Socket and Networking Security Hooks"
depends on SECURITY
If you are unsure how to answer this question, answer N.
+config SECURITY_LOWMEM
+ tristate "Low memory watermark support"
+ depends on SECURITY
+ help
+ Implements low memory watermark support
+
+ If you are unsure how to answer this question, answer N.
+
config SECURITY_DEFAULT_MMAP_MIN_ADDR
int "Low address space to protect from user allocation"
depends on SECURITY
obj-y += commoncap.o
# Object file lists
- obj-$(CONFIG_SECURITY) += security.o capability.o inode.o
+ obj-$(CONFIG_SECURITY) += security.o capability.o
+ obj-$(CONFIG_SECURITYFS) += inode.o
# Must precede capability.o in order to stack properly.
obj-$(CONFIG_SECURITY_SELINUX) += selinux/built-in.o
obj-$(CONFIG_SECURITY_SMACK) += smack/built-in.o
obj-$(CONFIG_SECURITY_ROOTPLUG) += root_plug.o
+obj-$(CONFIG_SECURITY_LOWMEM) += commoncap.o lowmem.o
obj-$(CONFIG_CGROUP_DEVICE) += device_cgroup.o
tristate
select SND_PCM
+ config SND_PXA2XX_LIB
+ tristate
+ select SND_AC97_CODEC if SND_PXA2XX_LIB_AC97
+
+ config SND_PXA2XX_LIB_AC97
+ bool
+
config SND_PXA2XX_AC97
tristate "AC97 driver for the Intel PXA2xx chip"
depends on ARCH_PXA
select SND_PXA2XX_PCM
select SND_AC97_CODEC
+ select SND_PXA2XX_LIB
+ select SND_PXA2XX_LIB_AC97
help
Say Y or M if you want to support any AC97 codec attached to
the PXA2xx AC97 interface.
-endif # SND_ARM
+config SND_OMAP_AIC23
+ tristate "OMAP AIC23 alsa driver (osk5912)"
+ depends on ARCH_OMAP && SND
+ select SND_PCM
- select I2C
- select I2C_OMAP if ARCH_OMAP
++ #select I2C
++ #select I2C_OMAP if ARCH_OMAP
+ select SENSORS_TLV320AIC23
+ help
+ Say Y here if you have a OSK platform board
+ and want to use its AIC23 audio chip.
+
+ To compile this driver as a module, choose M here: the module
+ will be called snd-omap-aic23.
+
+config SND_OMAP_TSC2101
+ tristate "OMAP TSC2101 alsa driver"
+ depends on ARCH_OMAP && SND
+ select SND_PCM
+ select SPI_TSC2101
+ help
+ Say Y here if you have a OMAP platform board
+ and want to use its TSC2101 audio chip. Driver has
+ been tested with H2 and iPAQ h6300.
+
+ To compile this driver as a module, choose M here: the module
+ will be called snd-omap-tsc2101.
+
+config SND_SX1
+ tristate "Siemens SX1 Egold alsa driver"
+ depends on ARCH_OMAP && SND
+ select SND_PCM
+ help
+ Say Y here if you have a OMAP310 based Siemens SX1.
+
+ To compile this driver as a module, choose M here: the module
+ will be called snd-omap-sx1.
+
+config SND_OMAP_TSC2102
+ tristate "OMAP TSC2102 alsa driver"
+ depends on ARCH_OMAP && SND
+ select SND_PCM
+ select SPI_TSC2102
+ help
+ Say Y here if you have an OMAP platform board
+ and want to use its TSC2102 audio chip.
+ To compile this driver as a module, choose M here: the module
+ will be called snd-omap-tsc2102.
+
+config SND_OMAP24XX_EAC
+ tristate "Audio driver for OMAP24xx EAC"
+ depends on SND
+ help
+ Audio driver for Enhanced Audio Controller found in TI's OMAP24xx
+ processors.
+
+ Currently contains only low-level support functions for
+ initializing EAC HW, creating ALSA sound card instance for it
+ and registering mixer controls implemented by a codec driver.
+ PCM stream is expected to be under DSP co-processor control.
+
+ To compile this driver as a module, choose M here: the module
+ will be called snd-omap24xx-eac.
+
+endif # SND_ARM
obj-$(CONFIG_SND_PXA2XX_PCM) += snd-pxa2xx-pcm.o
snd-pxa2xx-pcm-objs := pxa2xx-pcm.o
+ obj-$(CONFIG_SND_PXA2XX_LIB) += snd-pxa2xx-lib.o
+ snd-pxa2xx-lib-y := pxa2xx-pcm-lib.o
+ snd-pxa2xx-lib-$(CONFIG_SND_PXA2XX_LIB_AC97) += pxa2xx-ac97-lib.o
+
obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o
snd-pxa2xx-ac97-objs := pxa2xx-ac97.o
+
+obj-$(CONFIG_SND) += omap/
obj-$(CONFIG_SOUND_OSS) += sound.o
+obj-$(CONFIG_SOUND_OMAP) += omap-audio-dma-intfc.o omap-audio.o
+obj-$(CONFIG_SOUND_OMAP_TSC2101)+= omap-audio-tsc2101.o
+obj-$(CONFIG_SOUND_OMAP_AIC23) += omap-audio-aic23.o
+
# Please leave it as is, cause the link order is significant !
obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
- obj-$(CONFIG_SOUND_HAL2) += hal2.o
obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
obj-$(CONFIG_SOUND_PSS) += pss.o ad1848.o mpu401.o
obj-$(CONFIG_SOUND_TRIX) += trix.o ad1848.o sb_lib.o uart401.o
projects / linux-2.6-omap-h63xx.git / commitdiff