extern void probe_nr_irqs_gsi(void);
 
+extern int setup_ioapic_entry(int apic, int irq,
+                             struct IO_APIC_route_entry *entry,
+                             unsigned int destination, int trigger,
+                             int polarity, int vector);
+extern void ioapic_write_entry(int apic, int pin,
+                              struct IO_APIC_route_entry e);
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
 static const int timer_through_8259 = 0;
 
        io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 }
 
-static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
+void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 {
        unsigned long flags;
        spin_lock_irqsave(&ioapic_lock, flags);
                                              handle_edge_irq, "edge");
 }
 
-static int setup_ioapic_entry(int apic_id, int irq,
-                             struct IO_APIC_route_entry *entry,
-                             unsigned int destination, int trigger,
-                             int polarity, int vector)
+int setup_ioapic_entry(int apic_id, int irq,
+                      struct IO_APIC_route_entry *entry,
+                      unsigned int destination, int trigger,
+                      int polarity, int vector)
 {
        /*
         * add it to the IO-APIC irq-routing table: