]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
[ARM] 4147/1: AT91: Define Timer/Counter clocks.
authorAndrew Victor <andrew@sanpeople.com>
Thu, 8 Feb 2007 09:25:38 +0000 (10:25 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 8 Feb 2007 14:55:27 +0000 (14:55 +0000)
Define the Timer/Counter Unit clocks on the AT91RM9200, AT91SAM9260 and
AT91SAM9261 processors.

Original patch from David Brownell.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c

index 870d4a4eb806f128506a53302a57a62f2c17e166..2ddcdd69df7d2267df116131323797f89a8ca3fa 100644 (file)
@@ -117,6 +117,36 @@ static struct clk pioD_clk = {
        .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc3_clk = {
+       .name           = "tc3_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc4_clk = {
+       .name           = "tc4_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC4,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc5_clk = {
+       .name           = "tc5_clk",
+       .pmc_mask       = 1 << AT91RM9200_ID_TC5,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
@@ -132,7 +162,12 @@ static struct clk *periph_clocks[] __initdata = {
        &twi_clk,
        &spi_clk,
        // ssc 0 .. ssc2
-       // tc0 .. tc5
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
+       &tc3_clk,
+       &tc4_clk,
+       &tc5_clk,
        &ohci_clk,
        &ether_clk,
        // irq0 .. irq6
index ffc4c09447400764e98d26af24144bce69ac88e1..e03ee625f40c8399be7adc45e5adadacb1011884 100644 (file)
@@ -107,6 +107,21 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk ohci_clk = {
        .name           = "ohci_clk",
        .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
@@ -137,6 +152,21 @@ static struct clk usart5_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_US5,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc3_clk = {
+       .name           = "tc3_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc4_clk = {
+       .name           = "tc4_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc5_clk = {
+       .name           = "tc5_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
@@ -152,14 +182,18 @@ static struct clk *periph_clocks[] __initdata = {
        &spi0_clk,
        &spi1_clk,
        // ssc
-       // tc0 .. tc2
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
        &ohci_clk,
        &ether_clk,
        &isi_clk,
        &usart3_clk,
        &usart4_clk,
        &usart5_clk,
-       // tc3 .. tc5
+       &tc3_clk,
+       &tc4_clk,
+       &tc5_clk,
        // irq0 .. irq2
 };
 
index 47e02ff7e872bb097908f684fa0064b0ae74cb76..1a9102368f11ba035ada2b81c7b82cd4863c1c34 100644 (file)
@@ -97,6 +97,21 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk ohci_clk = {
        .name           = "ohci_clk",
        .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
@@ -121,7 +136,9 @@ static struct clk *periph_clocks[] __initdata = {
        &spi0_clk,
        &spi1_clk,
        // ssc 0 .. ssc2
-       // tc0 .. tc2
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
        &ohci_clk,
        &lcdc_clk,
        // irq0 .. irq2