struct net_device *dev_peer;
 
                dev_peer = pci_get_drvdata(tp->pdev_peer);
+               /* remove_one() may have been run on the peer. */
                if (!dev_peer)
-                       BUG();
-               tp_peer = netdev_priv(dev_peer);
+                       tp_peer = tp;
+               else
+                       tp_peer = netdev_priv(dev_peer);
        }
 
        if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 static int tg3_nvram_lock(struct tg3 *);
 static void tg3_nvram_unlock(struct tg3 *);
 
-static int tg3_set_power_state(struct tg3 *tp, int state)
+static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 {
        u32 misc_host_ctrl;
        u16 power_control, power_caps;
        power_control |= PCI_PM_CTRL_PME_STATUS;
        power_control &= ~(PCI_PM_CTRL_STATE_MASK);
        switch (state) {
-       case 0:
+       case PCI_D0:
                power_control |= 0;
                pci_write_config_word(tp->pdev,
                                      pm + PCI_PM_CTRL,
 
                return 0;
 
-       case 1:
+       case PCI_D1:
                power_control |= 1;
                break;
 
-       case 2:
+       case PCI_D2:
                power_control |= 2;
                break;
 
-       case 3:
+       case PCI_D3hot:
                power_control |= 3;
                break;
 
        int err;
 
        /* Force the chip into D0. */
-       err = tg3_set_power_state(tp, 0);
+       err = tg3_set_power_state(tp, PCI_D0);
        if (err)
                goto out;
 
 
        tg3_full_lock(tp, 0);
 
+       err = tg3_set_power_state(tp, PCI_D0);
+       if (err)
+               return err;
+
        tg3_disable_ints(tp);
        tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
 
        tp->tg3_flags &=
                ~(TG3_FLAG_INIT_COMPLETE |
                  TG3_FLAG_GOT_SERDES_FLOWCTL);
-       netif_carrier_off(tp->dev);
 
        tg3_full_unlock(tp);
 
 
        tg3_free_consistent(tp);
 
+       tg3_set_power_state(tp, PCI_D3hot);
+
+       netif_carrier_off(tp->dev);
+
        return 0;
 }
 
 
        memset(p, 0, TG3_REGDUMP_LEN);
 
+       if (tp->link_config.phy_is_low_power)
+               return;
+
        tg3_full_lock(tp, 0);
 
 #define __GET_REG32(reg)       (*(p)++ = tr32(reg))
        u8  *pd;
        u32 i, offset, len, val, b_offset, b_count;
 
+       if (tp->link_config.phy_is_low_power)
+               return -EAGAIN;
+
        offset = eeprom->offset;
        len = eeprom->len;
        eeprom->len = 0;
        u32 offset, len, b_offset, odd_len, start, end;
        u8 *buf;
 
+       if (tp->link_config.phy_is_low_power)
+               return -EAGAIN;
+
        if (eeprom->magic != TG3_EEPROM_MAGIC)
                return -EINVAL;
 
 {
        struct tg3 *tp = netdev_priv(dev);
 
+       if (tp->link_config.phy_is_low_power)
+               tg3_set_power_state(tp, PCI_D0);
+
        memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
 
        if (tg3_test_nvram(tp) != 0) {
 
                tg3_full_unlock(tp);
        }
+       if (tp->link_config.phy_is_low_power)
+               tg3_set_power_state(tp, PCI_D3hot);
+
 }
 
 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
                        break;                  /* We have no PHY */
 
+               if (tp->link_config.phy_is_low_power)
+                       return -EAGAIN;
+
                spin_lock_bh(&tp->lock);
                err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
                spin_unlock_bh(&tp->lock);
                if (!capable(CAP_NET_ADMIN))
                        return -EPERM;
 
+               if (tp->link_config.phy_is_low_power)
+                       return -EAGAIN;
+
                spin_lock_bh(&tp->lock);
                err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
                spin_unlock_bh(&tp->lock);
                tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
 
        /* Force the chip into D0. */
-       err = tg3_set_power_state(tp, 0);
+       err = tg3_set_power_state(tp, PCI_D0);
        if (err) {
                printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
                       pci_name(tp->pdev));
 
        pci_restore_state(tp->pdev);
 
-       err = tg3_set_power_state(tp, 0);
+       err = tg3_set_power_state(tp, PCI_D0);
        if (err)
                return err;