TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
                        TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
+               }
 
-                       if (data->link_up == 0) {
-                               /* The manual says it can take 3-4 usecs for the speed change
-                                * to take effect.
-                                */
-                               udelay(5);
+               if (data->link_up == 0) {
+                       /* The manual says it can take 3-4 usecs for the speed change
+                        * to take effect.
+                        */
+                       udelay(5);
 
-                               spin_lock(&data->txlock);
-                               if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
-                                       netif_wake_queue(dev);
+                       spin_lock(&data->txlock);
+                       if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
+                               netif_wake_queue(dev);
 
-                               data->link_up = 1;
-                               spin_unlock(&data->txlock);
-                       }
+                       data->link_up = 1;
+                       spin_unlock(&data->txlock);
                }
-
        } else {
                if (data->link_up == 1) {
                        netif_stop_queue(dev);
         * PHY_STAT register before the link up status bit is set.
         */
 
-       data->link_up = 1;
+       data->link_up = 0;
 
        while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
                 BMSR_LSTATUS)) {
                if (i++ > (MII_READ_DELAY / 10)) {
-                       data->link_up = 0;
                        break;
                }
                spin_unlock_irqrestore(&phy_lock, flags);