Merge git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] update memory attribute aliasing documentation & test cases
  [IA64] fail mmaps that span areas with incompatible attributes
  [IA64] allow WB /sys/.../legacy_mem mmaps
  [IA64] make ioremap avoid unsupported attributes
  [IA64] rename ioremap variables to match i386
  [IA64] relax per-cpu TLB requirement to DTC
  [IA64] remove per-cpu ia64_phys_stacked_size_p8
  [IA64] Fix example error injection program
  [IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface
  [IA64] Itanium MC Error Injection Tool: Makefile changes
  [IA64] Itanium MC Error Injection Tool: Driver sysfs interface
  [IA64] Itanium MC Error Injection Tool: Doc and sample application
  [IA64] Itanium MC Error Injection Tool: Kernel configuration

diff --combined arch/ia64/Kconfig
index 3b71f97d0b603a7a3b112e9ea1561eab06e6265f,09866581a3266f90ffab3160812ace8b332efdaf..e23af4b6ae8c173ee20b456805bd556ac86a83fb
--- 1/arch/ia64/Kconfig
--- 2/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@@ -14,7 -14,6 +14,7 @@@ config IA6
        select PCI if (!IA64_HP_SIM)
        select ACPI if (!IA64_HP_SIM)
        select PM if (!IA64_HP_SIM)
 +      select ARCH_SUPPORTS_MSI
        default y
        help
          The Itanium Processor Family is Intel's 64-bit successor to
@@@ -439,6 -438,16 +439,16 @@@ config IA64_PALINF
          To use this option, you have to ensure that the "/proc file system
          support" (CONFIG_PROC_FS) is enabled, too.
  
+ config IA64_MC_ERR_INJECT
+       tristate "MC error injection support"
+       help
+         Selets whether support for MC error injection. By enabling the
+         support, kernel provide sysfs interface for user application to
+         call MC error injection PAL procedure to inject various errors.
+         This is a useful tool for MCA testing.
+ 
+         If you're unsure, do not select this option.
+ 
  config SGI_SN
        def_bool y if (IA64_SGI_SN2 || IA64_GENERIC)
  

diff --combined arch/ia64/mm/init.c
index 2da841110727b223c4e9c4720a6351a94c92a7c1,5b70241741b4a163233439dd89ca70c04a4a6ddc..cffb1e8325e8e226fdde5e996f33aad425bf6006
--- 1/arch/ia64/mm/init.c
--- 2/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@@ -121,7 -121,7 +121,7 @@@ lazy_mmu_prot_update (pte_t pte
                return;                         /* i-cache is already coherent with d-cache */
  
        if (PageCompound(page)) {
 -              order = (unsigned long) (page[1].lru.prev);
 +              order = compound_order(page);
                flush_icache_range(addr, addr + (1UL << order << PAGE_SHIFT));
        }
        else
@@@ -355,7 -355,7 +355,7 @@@ setup_gate (void
  void __devinit
  ia64_mmu_init (void *my_cpu_data)
  {
-       unsigned long psr, pta, impl_va_bits;
+       unsigned long pta, impl_va_bits;
        extern void __devinit tlb_init (void);
  
  #ifdef CONFIG_DISABLE_VHPT
@@@ -364,15 -364,6 +364,6 @@@
  #     define VHPT_ENABLE_BIT  1
  #endif
  
-       /* Pin mapping for percpu area into TLB */
-       psr = ia64_clear_ic();
-       ia64_itr(0x2, IA64_TR_PERCPU_DATA, PERCPU_ADDR,
-                pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)),
-                PERCPU_PAGE_SHIFT);
- 
-       ia64_set_psr(psr);
-       ia64_srlz_i();
- 
        /*
         * Check if the virtually mapped linear page table (VMLPT) overlaps with a mapped
         * address space.  The IA-64 architecture guarantees that at least 50 bits of