]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
authorLinus Torvalds <torvalds@woody.linux-foundation.org>
Tue, 13 Nov 2007 17:04:03 +0000 (09:04 -0800)
committerLinus Torvalds <torvalds@woody.linux-foundation.org>
Tue, 13 Nov 2007 17:04:03 +0000 (09:04 -0800)
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  [POWERPC] Silence an annoying boot message
  [POWERPC] Fix early btext debug on PowerMac
  [POWERPC] Demote clockevent printk to KERN_DEBUG
  [POWERPC] Fix CONFIG_SMP=n build error on ppc64
  [POWERPC] Avoid unpaired stwcx. on some processors
  [POWERPC] Fix oops related to 4xx flush_tlb_page modification
  [POWERPC] cpm: Fix a couple minor issues in cpm_common.c.
  [POWERPC] Add -mno-spe for ARCH=powerpc builds

arch/powerpc/Makefile
arch/powerpc/kernel/btext.c
arch/powerpc/kernel/entry_32.S
arch/powerpc/kernel/time.c
arch/powerpc/mm/init_64.c
arch/powerpc/mm/tlb_64.c
arch/powerpc/sysdev/cpm_common.c
arch/ppc/kernel/entry.S
include/asm-powerpc/cputable.h
include/asm-powerpc/tlbflush.h

index 4e165342210aa84b508a91e11ef6a8c44148b980..bd87626c1f6041664ed777fcd4349116bb32ea32 100644 (file)
@@ -107,6 +107,9 @@ endif
 # No AltiVec instruction when building kernel
 KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
 
+# No SPE instruction when building kernel
+KBUILD_CFLAGS += $(call cc-option,-mno-spe)
+
 # Enable unit-at-a-time mode when possible. It shrinks the
 # kernel considerably.
 KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time)
index 3ef51fb6f107a57d3ca82f4c18ddfd84f689ce3a..9c74fdf29eeccc8f5c56adb7b1a5c98fc09a21e3 100644 (file)
@@ -186,7 +186,9 @@ int btext_initialize(struct device_node *np)
                pitch = *prop;
        if (pitch == 1)
                pitch = 0x1000;
-       prop = of_get_property(np, "address", NULL);
+       prop = of_get_property(np, "linux,bootx-addr", NULL);
+       if (prop == NULL)
+               prop = of_get_property(np, "address", NULL);
        if (prop)
                address = *prop;
 
index a7572cf464bd3bd861f5bb0283aaeed4fcfdecb0..69a91bd46115e171bb73cf76282db673ce5d054e 100644 (file)
@@ -251,6 +251,9 @@ syscall_exit_cont:
        bne-    2f
 1:
 #endif /* CONFIG_44x */
+BEGIN_FTR_SECTION
+       lwarx   r7,0,r1
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
        stwcx.  r0,0,r1                 /* to clear the reservation */
        lwz     r4,_LINK(r1)
        lwz     r5,_CCR(r1)
@@ -717,6 +720,9 @@ restore:
        mtctr   r11
 
        PPC405_ERR77(0,r1)
+BEGIN_FTR_SECTION
+       lwarx   r11,0,r1
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
        stwcx.  r0,0,r1                 /* to clear the reservation */
 
 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
index 4beb6329dfb7f9158b651d9abfcb2951465e00b8..c0d77723ba1141124733e05ab64b93343957a7fe 100644 (file)
@@ -829,7 +829,7 @@ static void register_decrementer_clockevent(int cpu)
        *dec = decrementer_clockevent;
        dec->cpumask = cpumask_of_cpu(cpu);
 
-       printk(KERN_INFO "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n",
+       printk(KERN_DEBUG "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n",
               dec->name, dec->mult, dec->shift, cpu);
 
        clockevents_register_device(dec);
index d9c82d3d64821d4ed15fa48ec745ebb39d9fccb8..c0f5cff77035e8d1abae6fe746e96af2cbcd6dd2 100644 (file)
@@ -19,8 +19,6 @@
  *
  */
 
-#undef DEBUG
-
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 
 #include "mmu_decl.h"
 
-#ifdef DEBUG
-#define DBG(fmt...) printk(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
 #if PGTABLE_RANGE > USER_VSID_RANGE
 #warning Limited user VSID range means pagetable space is wasted
 #endif
@@ -175,8 +167,8 @@ void pgtable_cache_init(void)
                int size = pgtable_cache_size[i];
                const char *name = pgtable_cache_name[i];
 
-               DBG("Allocating page table cache %s (#%d) "
-                   "for size: %08x...\n", name, i, size);
+               pr_debug("Allocating page table cache %s (#%d) "
+                       "for size: %08x...\n", name, i, size);
                pgtable_cache[i] = kmem_cache_create(name,
                                                     size, size,
                                                     SLAB_PANIC,
@@ -239,8 +231,8 @@ int __meminit vmemmap_populate(struct page *start_page,
                if (!p)
                        return -ENOMEM;
 
-               printk(KERN_WARNING "vmemmap %08lx allocated at %p, "
-                                   "physical %08lx.\n", start, p, __pa(p));
+               pr_debug("vmemmap %08lx allocated at %p, physical %08lx.\n",
+                       start, p, __pa(p));
 
                mapped = htab_bolt_mapping(start, start + page_size,
                                        __pa(p), mode_rw, mmu_linear_psize,
index eafbca52bff9ce1e4e58cc23d5ff03943434e6a0..e2d867ce1c7eb46fb259993ebf8f99c0a177bca9 100644 (file)
@@ -54,12 +54,10 @@ unsigned long pte_freelist_forced_free;
        ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
          / sizeof(pgtable_free_t))
 
-#ifdef CONFIG_SMP
 static void pte_free_smp_sync(void *arg)
 {
        /* Do nothing, just ensure we sync with all CPUs */
 }
-#endif
 
 /* This is only called when we are critically out of memory
  * (and fail to get a page in pte_free_tlb).
index 66c8ad4cfce64075a52044238eab4b98ed28b0f8..165981c87786bc2832e2f7bef8436a69663c88de 100644 (file)
@@ -77,8 +77,6 @@ int __init cpm_muram_init(void)
        int i = 0;
        int ret = 0;
 
-       printk("cpm_muram_init\n");
-
        spin_lock_init(&cpm_muram_lock);
        /* initialize the info header */
        rh_init(&cpm_muram_info, 1,
@@ -193,7 +191,7 @@ void __iomem *cpm_muram_addr(unsigned long offset)
 EXPORT_SYMBOL(cpm_muram_addr);
 
 /**
- * cpm_muram_phys - turn a muram virtual address into a DMA address
+ * cpm_muram_dma - turn a muram virtual address into a DMA address
  * @offset: virtual address from cpm_muram_addr() to convert
  */
 dma_addr_t cpm_muram_dma(void __iomem *addr)
index b19bfef2034dbb67c737b7388ea5d92bcdcae0d4..59e77eb63338de4ea3bab18462967a6e16d4b208 100644 (file)
@@ -251,6 +251,9 @@ syscall_exit_cont:
        bne-    2f
 1:
 #endif /* CONFIG_44x */
+BEGIN_FTR_SECTION
+       lwarx   r7,0,r1
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
        stwcx.  r0,0,r1                 /* to clear the reservation */
        lwz     r4,_LINK(r1)
        lwz     r5,_CCR(r1)
@@ -713,6 +716,9 @@ restore:
        mtctr   r11
 
        PPC405_ERR77(0,r1)
+BEGIN_FTR_SECTION
+       lwarx   r11,0,r1
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
        stwcx.  r0,0,r1                 /* to clear the reservation */
 
 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
index 9d74338e3dec05bcd4ce93090fe365ba8279f1e1..4525c784dfd08d31ad7734a3b50fe4d42151683c 100644 (file)
@@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_FPU_UNAVAILABLE                ASM_CONST(0x0000000000800000)
 #define CPU_FTR_UNIFIED_ID_CACHE       ASM_CONST(0x0000000001000000)
 #define CPU_FTR_SPE                    ASM_CONST(0x0000000002000000)
+#define CPU_FTR_NEED_PAIRED_STWCX      ASM_CONST(0x0000000004000000)
 
 /*
  * Add the 64-bit processor unique features in the top half of the word;
@@ -261,25 +262,25 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_7450_20       (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7450_21       (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7450_23       (CPU_FTR_COMMON | \
-           CPU_FTR_USE_TB | \
+           CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7455_1        (CPU_FTR_COMMON | \
-           CPU_FTR_USE_TB | \
+           CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7455_20       (CPU_FTR_COMMON | \
-           CPU_FTR_USE_TB | \
+           CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
@@ -289,31 +290,32 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7447_10       (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
+           CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7447  (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+           CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_7448  (CPU_FTR_COMMON | \
            CPU_FTR_USE_TB | \
            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-           CPU_FTR_PPC_LE)
+           CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 #define CPU_FTRS_82XX  (CPU_FTR_COMMON | \
            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
index e7b4c0d298aecff4ff708d7ef3be46bbb0608dd8..5c91081476441277c968d0f55067442d4cd20640 100644 (file)
@@ -44,13 +44,13 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 static inline void flush_tlb_page(struct vm_area_struct *vma,
                                  unsigned long vmaddr)
 {
-       _tlbie(vmaddr, vma->vm_mm->context.id);
+       _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
 }
 
 static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
                                         unsigned long vmaddr)
 {
-       _tlbie(vmaddr, vma->vm_mm->context.id);
+       _tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
 }
 
 static inline void flush_tlb_range(struct vm_area_struct *vma,