kinfo->spi_piocnt = dd->ipath_pbufsport;
                kinfo->spi_piobufbase = (u64) pd->port_piobufs;
                kinfo->__spi_uregbase = (u64) dd->ipath_uregbase +
-                       dd->ipath_palign * pd->port_port;
+                       dd->ipath_ureg_align * pd->port_port;
        } else if (master) {
                kinfo->spi_piocnt = (dd->ipath_pbufsport / subport_cnt) +
                                    (dd->ipath_pbufsport % subport_cnt);
        }
        if (shared) {
                kinfo->spi_port_uregbase = (u64) dd->ipath_uregbase +
-                       dd->ipath_palign * pd->port_port;
+                       dd->ipath_ureg_align * pd->port_port;
                kinfo->spi_port_rcvegrbuf = kinfo->spi_rcv_egrbufs;
                kinfo->spi_port_rcvhdr_base = kinfo->spi_rcvhdr_base;
                kinfo->spi_port_rcvhdr_tailaddr = kinfo->spi_rcvhdr_tailaddr;
                goto bail;
        }
 
-       ureg = dd->ipath_uregbase + dd->ipath_palign * pd->port_port;
+       ureg = dd->ipath_uregbase + dd->ipath_ureg_align * pd->port_port;
        if (!pd->port_subport_cnt) {
                /* port is not shared */
                piocnt = dd->ipath_pbufsport;
 
                              dd->ipath_htspeed);
        ret = 0;
 
+       /*
+        * set here, not in ipath_init_*_funcs because we have to do
+        * it after we can read chip registers.
+        */
+       dd->ipath_ureg_align =
+               ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
+
 bail:
        return ret;
 }
 
                        dd->ipath_f_put_tid = ipath_pe_put_tid_2;
        }
 
+
+       /*
+        * set here, not in ipath_init_*_funcs because we have to do
+        * it after we can read chip registers.
+        */
+       dd->ipath_ureg_align =
+               ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
+
        return ret;
 }
 
 
        void *ipath_dummy_hdrq; /* used after port close */
        dma_addr_t ipath_dummy_hdrq_phys;
 
+       unsigned long ipath_ureg_align; /* user register alignment */
+
        /*
         * Shadow copies of registers; size indicates read access size.
         * Most of them are readonly, but some are write-only register,
        return readl(regno + (u64 __iomem *)
                     (dd->ipath_uregbase +
                      (char __iomem *)dd->ipath_kregbase +
-                     dd->ipath_palign * port));
+                     dd->ipath_ureg_align * port));
 }
 
 /**
 {
        u64 __iomem *ubase = (u64 __iomem *)
                (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
-                dd->ipath_palign * port);
+                dd->ipath_ureg_align * port);
        if (dd->ipath_kregbase)
                writeq(value, &ubase[regno]);
 }