since we have this always turned on now and dont want it off (and hasnt been an option in a while)
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
        bool
        default y
 
-config IRQCHIP_DEMUX_GPIO
-       bool
-       depends on (BF52x || BF53x || BF561 || BF54x)
-       default y
-
 source "init/Kconfig"
 source "kernel/Kconfig.preempt"
 
 
                .end = IRQ_PROG_INTB,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
        }, {
-               /*
-                *  denotes the flag pin and is used directly if
-                *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
-                */
                .start = IRQ_PF7,
                .end = IRQ_PF7,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 
                .end = IRQ_PROG_INTB,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
        }, {
-               /*
-                *  denotes the flag pin and is used directly if
-                *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
-                */
                .start = IRQ_PF7,
                .end = IRQ_PF7,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 
                .end = IRQ_PROG_INTB,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
        }, {
-               /*
-                *  denotes the flag pin and is used directly if
-                *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
-                */
                .start = IRQ_PF9,
                .end = IRQ_PF9,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 
                .end    = IRQ_PROG_INTB,
                .flags  = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
        }, {
-               /*
-                *  denotes the flag pin and is used directly if
-                *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
-                */
                .start  = IRQ_PF7,
                .end    = IRQ_PF7,
                .flags  = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
 
        .unmask = bf561_internal_unmask_irq,
 };
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
 
 
 }
 
-#endif                         /* CONFIG_IRQCHIP_DEMUX_GPIO */
-
 void __init init_exception_vectors(void)
 {
        SSYNC();
                        set_irq_chip(irq, &bf561_core_irqchip);
                else
                        set_irq_chip(irq, &bf561_internal_irqchip);
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+
                if ((irq != IRQ_PROG0_INTA) &&
-                   (irq != IRQ_PROG1_INTA) && (irq != IRQ_PROG2_INTA)) {
-#endif
+                   (irq != IRQ_PROG1_INTA) &&
+                   (irq != IRQ_PROG2_INTA))
                        set_irq_handler(irq, handle_simple_irq);
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
-               } else {
+               else
                        set_irq_chained_handler(irq, bf561_demux_gpio_irq);
-               }
-#endif
-
        }
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
        for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
                set_irq_chip(irq, &bf561_gpio_irqchip);
                /* if configured as edge, then will be changed to do_edge_IRQ */
                set_irq_handler(irq, handle_level_irq);
        }
-#endif
+
        bfin_write_IMASK(0);
        CSYNC();
        ilat = bfin_read_ILAT();
 }
 
 #ifdef CONFIG_DO_IRQ_L1
-void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text));
+__attribute__((l1_text))
 #endif
-
 void do_irq(int vec, struct pt_regs *fp)
 {
        if (vec == EVT_IVTMR_P) {
 
 }
 #endif                         /* BF537_GENERIC_ERROR_INT_DEMUX */
 
-#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
+#if !defined(CONFIG_BF54x)
 
 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
        }
 }
 
-#else                          /* CONFIG_IRQCHIP_DEMUX_GPIO */
+#else                          /* CONFIG_BF54x */
 
 #define NR_PINT_SYS_IRQS       4
 #define NR_PINT_BITS           32
        }
 
 }
-#endif                         /* CONFIG_IRQCHIP_DEMUX_GPIO */
+#endif
 
 void __init init_exception_vectors(void)
 {
        bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
        bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
        bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
-#ifdef CONFIG_BF54x
+# ifdef CONFIG_BF54x
        bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
        bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
-#endif
+# endif
 #else
        bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
        bfin_write_SIC_IWR(IWR_ENABLE_ALL);
 
        local_irq_disable();
 
-#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
-#ifdef CONFIG_PINTx_REASSIGN
+#ifdef CONFIG_BF54x
+# ifdef CONFIG_PINTx_REASSIGN
        pint[0]->assign = CONFIG_PINT0_ASSIGN;
        pint[1]->assign = CONFIG_PINT1_ASSIGN;
        pint[2]->assign = CONFIG_PINT2_ASSIGN;
        pint[3]->assign = CONFIG_PINT3_ASSIGN;
-#endif
+# endif
        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
        init_pint_lut();
 #endif
 #endif
 
                        switch (irq) {
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #if defined(CONFIG_BF53x)
                        case IRQ_PROG_INTA:
                                set_irq_chained_handler(irq,
                                                        bfin_demux_gpio_irq);
                                break;
-#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
+# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
                        case IRQ_MAC_RX:
                                set_irq_chained_handler(irq,
                                                        bfin_demux_gpio_irq);
                                break;
-#endif
+# endif
 #elif defined(CONFIG_BF54x)
                        case IRQ_PINT0:
                                set_irq_chained_handler(irq,
                                set_irq_chained_handler(irq,
                                                        bfin_demux_gpio_irq);
                                break;
-#endif
 #endif
                        default:
                                set_irq_handler(irq, handle_simple_irq);
        }
 #endif
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #ifndef CONFIG_BF54x
        for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
 #else
                /* if configured as edge, then will be changed to do_edge_IRQ */
                set_irq_handler(irq, handle_level_irq);
        }
-#endif
+
        bfin_write_IMASK(0);
        CSYNC();
        ilat = bfin_read_ILAT();
 }
 
 #ifdef CONFIG_DO_IRQ_L1
-void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
+__attribute__((l1_text))
 #endif
-
 void do_irq(int vec, struct pt_regs *fp)
 {
        if (vec == EVT_IVTMR_P) {
 
 
 #define GPIO_IRQ_BASE  IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
 
 
 #define GPIO_IRQ_BASE          IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define        NR_IRQS         (IRQ_PF15+1)
-#else
-#define        NR_IRQS         SYS_IRQS
-#endif
 
 #define IVG7                   7
 #define IVG8                   8
 
 
 #define GPIO_IRQ_BASE  IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
-#else
-#define NR_IRQS     (IRQ_UART1_ERROR+1)
-#endif
 
 #define IVG7            7
 #define IVG8            8
 
 
 #define GPIO_IRQ_BASE  IRQ_PA0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PJ15+1)
-#else
-#define NR_IRQS     (SYS_IRQS+1)
-#endif
 
 /* For compatibility reasons with existing code */
 
 
 
 #define GPIO_IRQ_BASE          IRQ_PF0
 
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS                        (IRQ_PF47 + 1)
-#else
-#define NR_IRQS                        SYS_IRQS
-#endif
 
 #define IVG7                   7
 #define IVG8                   8