*
* This file implements a DMA interface using TI's CPPI DMA.
* For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB.
- * TUSB 6010 over VLYNQ has CPPI that looks much like DaVinci.
+ * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
*/
#include <linux/usb.h>
#include "cppi_dma.h"
-/* CPPI DMA status 7-mar:
+/* CPPI DMA status 7-mar-2006:
*
* - See musb_{host,gadget}.c for more info
*
* - Correct RX DMA generally forces the engine into irq-per-packet mode,
* which can easily saturate the CPU under non-mass-storage loads.
*
- * NOTES 24-aug (2.6.18-rc4):
+ * NOTES 24-aug-2006 (2.6.18-rc4):
*
* - peripheral RXDMA wedged in a test with packets of length 512/512/1.
* evidently after the 1 byte packet was received and acked, the queue
* ========
* TX is a lot more reasonable than RX; it doesn't need to run in
* irq-per-packet mode very often. RNDIS mode seems to behave too
- * (other how it handles the exactly-N-packets case). Building a
+ * (except how it handles the exactly-N-packets case). Building a
* txdma queue with multiple requests (urb or usb_request) looks
* like it would work ... but fault handling would need much testing.
*
struct cppi;
-/**
- * Channel Control Structure
- *
- * CPPI Channel Control structure. Using he same for Tx/Rx. If need be
- * derive out of this later.
- */
+/* CPPI Channel Control structure */
struct cppi_channel {
/* First field must be dma_channel for easy type casting
* FIXME just use container_of() and be typesafe instead!
*/
struct dma_channel Channel;
- /* back pointer to the Dma Controller structure */
+ /* back pointer to the DMA Controller structure */
struct cppi *controller;
/* which direction of which endpoint? */
struct list_head tx_complete;
};
-/**
- * CPPI Dma Controller Object
- *
- * CPPI Dma controller object.Encapsulates all bookeeping and Data
- * structures pertaining to the CPPI Dma Controller.
- */
+/* CPPI DMA controller object */
struct cppi {
struct dma_controller Controller;
struct musb *musb;
{
/* start the on-chip PHY and its PLL */
__raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
- IO_ADDRESS(USBPHY_CTL_PADDR));
- while ((__raw_readl(IO_ADDRESS(USBPHY_CTL_PADDR))
+ (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
+ while ((__raw_readl((void __force __iomem *)
+ IO_ADDRESS(USBPHY_CTL_PADDR))
& USBPHY_PHYCLKGD) == 0)
cpu_relax();
}
static inline void phy_off(void)
{
/* powerdown the on-chip PHY and its oscillator */
- __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN,
+ __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
IO_ADDRESS(USBPHY_CTL_PADDR));
}
davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state);
vbus_state = !vbus_state;
}
-DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
+static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
#endif /* modified board */
#endif /* EVM */
static void davinci_set_vbus(struct musb *musb, int is_on)
{
WARN_ON(is_on && is_peripheral_active(musb));
- return davinci_source_power(musb, is_on, 0);
+ davinci_source_power(musb, is_on, 0);
}
static void otg_timer(unsigned long _musb)
{
struct musb *musb = (void *)_musb;
- void *__iomem mregs = musb->mregs;
+ void __iomem *mregs = musb->mregs;
u8 devctl;
unsigned long flags;
unsigned long flags;
irqreturn_t retval = IRQ_NONE;
struct musb *musb = __hci;
- void *__iomem tibase = musb->ctrl_base;
+ void __iomem *tibase = musb->ctrl_base;
u32 tmp;
spin_lock_irqsave(&musb->lock, flags);
*/
if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
- void *__iomem mregs = musb->mregs;
+ void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
int err = musb->int_usb & MUSB_INTR_VBUSERROR;
* to get VBUS errors during enumeration.
*
* This is a workaround, but newer RTL from Mentor
- * seems to lalow a better one: "re"starting sessions
+ * seems to allow a better one: "re"starting sessions
* without waiting (on EVM, a **long** time) for VBUS
* to stop registering in devctl.
*/
int __init musb_platform_init(struct musb *musb)
{
- void *__iomem tibase = musb->ctrl_base;
- u32 revision;
+ void __iomem *tibase = musb->ctrl_base;
+ u32 revision;
musb->mregs += DAVINCI_BASE_OFFSET;
#if 0
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
- revision,
- __raw_readl((void *__iomem) IO_ADDRESS(USBPHY_CTL_PADDR)),
+ revision, __raw_readl((void __force __iomem *)
+ IO_ADDRESS(USBPHY_CTL_PADDR)),
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
musb->isr = davinci_interrupt;
#define DAVINCI_DMA_ALL_CHANNELS_ENABLE 0xF
#define DAVINCI_DMA_ALL_CHANNELS_DISABLE 0xF
-/* REVISIT relying on "volatile" here is wrong ... */
+/* FIXME relying on "volatile" here is wrong ... */
/* define structures of Rx/Tx stateRam entries */
struct cppi_tx_stateram {
#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
-#define MUSB_VERSION_BASE "2.2a/db-0.5.2"
+#define MUSB_VERSION_BASE "6.0"
#ifndef MUSB_VERSION_SUFFIX
#define MUSB_VERSION_SUFFIX ""
#include "musb_core.h"
-/* MUSB PERIPHERAL status 3-mar:
+/* MUSB PERIPHERAL status 3-mar-2006:
*
* - EP0 seems solid. It passes both USBCV and usbtest control cases.
* Minor glitches:
* + TUSB 6010, platform-specific dma in the works
*/
-/**************************************************************************
-Handling completion
-**************************************************************************/
+/* ----------------------------------------------------------------------- */
/*
* Immediately complete a request.
}
}
-/**************************************************************************
- * TX/IN and RX/OUT Data transfers
- **************************************************************************/
+/* ----------------------------------------------------------------------- */
+
+/* Data transfers - pure PIO, pure DMA, or mixed mode */
/*
* This assumes the separate CPPI engine is responding to DMA requests
.fifo_flush = musb_gadget_fifo_flush
};
-/***********************************************************************/
+/* ----------------------------------------------------------------------- */
static int musb_gadget_get_frame(struct usb_gadget *gadget)
{
.pullup = musb_gadget_pullup,
};
-/****************************************************************
- * Registration operations
- ****************************************************************/
+/* ----------------------------------------------------------------------- */
+
+/* Registration */
/* Only this registration code "knows" the rule (from USB standards)
* about there being only one external upstream port. It assumes
EXPORT_SYMBOL(usb_gadget_unregister_driver);
-/***********************************************************************/
+/* ----------------------------------------------------------------------- */
/* lifecycle operations called through plat_uds.c */
/*
- * MUSB OTG driver ep0 handling
+ * MUSB OTG peripheral driver ep0 handling
*
* Copyright 2005 Mentor Graphics Corporation
* Copyright (C) 2005-2006 by Texas Instruments
.queue = musb_g_ep0_queue,
.dequeue = musb_g_ep0_dequeue,
.set_halt = musb_g_ep0_halt,
- .fifo_status = NULL,
- .fifo_flush = NULL,
};
*
* - Not tested with HNP, but some SRP paths seem to behave.
*
- * NOTE 24-August:
+ * NOTE 24-August-2006:
*
* - Bulk traffic finally uses both sides of hardware ep1, freeing up an
* extra endpoint for periodic use enabling hub + keybd + mouse. That
*/
-/*************************** Forwards ***************************/
-
static void musb_ep_program(struct musb *musb, u8 epnum,
struct urb *urb, unsigned int nOut,
u8 * buf, u32 len);
/* general endpoint setup */
if (epnum) {
- u16 csr = csr;
-
/* ASSERT: TXCSR_DMAENAB was already cleared */
/* flush all old state, set default */
return (void *) hcd->hcd_priv;
}
-/* stored in "usb_host_endpoint.hcpriv" for scheduled endpoints
- */
+/* stored in "usb_host_endpoint.hcpriv" for scheduled endpoints */
struct musb_qh {
struct usb_host_endpoint *hep; /* usbcore info */
struct usb_device *dev;
/*
- * MUSB OTG driver Linux-specific architecture defines
+ * MUSB OTG driver register I/O
*
* Copyright 2005 Mentor Graphics Corporation
* Copyright (C) 2005-2006 by Texas Instruments
*
*/
-/*
- * Inventra Controller Driver (ICD) for Linux.
- *
- * The code managing debug files (currently in procfs).
- */
-
#include <linux/kernel.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
return buf - aBuffer;
}
-/** Dump the current status and compile options.
+/* Dump the current status and compile options.
* @param musb the device driver instance
* @param buffer where to dump the status; it must be big enough hold the
* result otherwise "BAD THINGS HAPPENS(TM)".
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
code = sprintf(buffer, "Peripheral address: %02x\n",
- musb_readb(musb, MUSB_FADDR));
+ musb_readb(musb->ctrl_base, MUSB_FADDR));
if (code <= 0)
goto done;
buffer += code;
"\n",
musb_readl(musb->ctrl_base, DAVINCI_USB_CTRL_REG),
musb_readl(musb->ctrl_base, DAVINCI_USB_STAT_REG),
- __raw_readl(IO_ADDRESS(USBPHY_CTL_PADDR)),
+ __raw_readl((void __force __iomem *)
+ IO_ADDRESS(USBPHY_CTL_PADDR)),
musb_readl(musb->ctrl_base, DAVINCI_RNDIS_REG),
musb_readl(musb->ctrl_base, DAVINCI_AUTOREQ_REG),
musb_readl(musb->ctrl_base,
/*
- * MUSB OTG driver virtual hub support
+ * MUSB OTG driver virtual root hub support
*
* Copyright 2005 Mentor Graphics Corporation
* Copyright (C) 2005-2006 by Texas Instruments
/*
- * MUSB OTG driver internal DMA controller support
+ * MUSB OTG driver - support for Mentor's DMA controller
*
* Copyright 2005 Mentor Graphics Corporation
* Copyright (C) 2005-2007 by Texas Instruments
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
-
-/*
- * Implementation for the DMA controller within the MUSBMHDRC.
- */
-
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
projects / linux-2.6-omap-h63xx.git / commitdiff