CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
        /* L4 domain clocks */
        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
+       CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
        /* virtual meta-group clock */
        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
        /* general l4 interface ck, multi-parent functional clk */
 
        .set_rate       = &omap2_clksel_set_rate
 };
 
+/*
+ * Presumably this is the same as SSI_ICLK.
+ * TRM contradicts itself on what clockdomain SSI_ICLK is in
+ */
+static struct clk ssi_l4_ick = {
+       .name           = "ssi_l4_ick",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &l4_ck,
+       .clkdm_name     = "core_l4_clkdm",
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+       .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+       .recalc         = &followparent_recalc,
+};
+
 
 /*
  * GFX clock domain