Re-posting DMA Macros updated to use DMA V4 baseaddress

Modified DMA macros to use DMA V4 Base, to support all DMA V4 based OMAP
platforms.

Signed-off-by: Syed Mohammed Khasim <x0khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 05a38498cbe06c3527260a12186fda3d2732a7fc..3e026b20464f45d859787ada256e2e54443206a8 100644 (file)
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -628,7 +628,7 @@ void omap_clear_dma(int lch)
 
        if (cpu_is_omap24xx()) {
                int i;
-               u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
+               u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
                for (i = 0; i < 0x44; i += 4)
                        omap_writel(0, lch_base + i);
        }

diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f33b467fddb7c871b4cfd275423cccaeded2375d..a20631b8a552439d1149521c25e1bfbbda1c9bb6 100644 (file)
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -45,22 +45,22 @@
 #define OMAP_DMA_PCHD_SR               (OMAP_DMA_BASE + 0x4c0)
 
 /* Hardware registers for omap2 */
-#define OMAP24XX_DMA_BASE              (L4_24XX_BASE + 0x56000)
-#define OMAP_DMA4_REVISION             (OMAP24XX_DMA_BASE + 0x00)
-#define OMAP_DMA4_GCR_REG              (OMAP24XX_DMA_BASE + 0x78)
-#define OMAP_DMA4_IRQSTATUS_L0         (OMAP24XX_DMA_BASE + 0x08)
-#define OMAP_DMA4_IRQSTATUS_L1         (OMAP24XX_DMA_BASE + 0x0c)
-#define OMAP_DMA4_IRQSTATUS_L2         (OMAP24XX_DMA_BASE + 0x10)
-#define OMAP_DMA4_IRQSTATUS_L3         (OMAP24XX_DMA_BASE + 0x14)
-#define OMAP_DMA4_IRQENABLE_L0         (OMAP24XX_DMA_BASE + 0x18)
-#define OMAP_DMA4_IRQENABLE_L1         (OMAP24XX_DMA_BASE + 0x1c)
-#define OMAP_DMA4_IRQENABLE_L2         (OMAP24XX_DMA_BASE + 0x20)
-#define OMAP_DMA4_IRQENABLE_L3         (OMAP24XX_DMA_BASE + 0x24)
-#define OMAP_DMA4_SYSSTATUS            (OMAP24XX_DMA_BASE + 0x28)
-#define OMAP_DMA4_CAPS_0               (OMAP24XX_DMA_BASE + 0x64)
-#define OMAP_DMA4_CAPS_2               (OMAP24XX_DMA_BASE + 0x6c)
-#define OMAP_DMA4_CAPS_3               (OMAP24XX_DMA_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4               (OMAP24XX_DMA_BASE + 0x74)
+#define OMAP_DMA4_BASE                 (L4_OMAP_BASE + 0x56000)
+#define OMAP_DMA4_REVISION             (OMAP_DMA4_BASE + 0x00)
+#define OMAP_DMA4_GCR_REG              (OMAP_DMA4_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L0         (OMAP_DMA4_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L1         (OMAP_DMA4_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L2         (OMAP_DMA4_BASE + 0x10)
+#define OMAP_DMA4_IRQSTATUS_L3         (OMAP_DMA4_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L0         (OMAP_DMA4_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L1         (OMAP_DMA4_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L2         (OMAP_DMA4_BASE + 0x20)
+#define OMAP_DMA4_IRQENABLE_L3         (OMAP_DMA4_BASE + 0x24)
+#define OMAP_DMA4_SYSSTATUS            (OMAP_DMA4_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0               (OMAP_DMA4_BASE + 0x64)
+#define OMAP_DMA4_CAPS_2               (OMAP_DMA4_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_3               (OMAP_DMA4_BASE + 0x70)
+#define OMAP_DMA4_CAPS_4               (OMAP_DMA4_BASE + 0x74)
 
 #ifdef CONFIG_ARCH_OMAP1
 
@@ -86,19 +86,19 @@
 #define OMAP_LOGICAL_DMA_CH_COUNT      32      /* REVISIT: Is this 32 + 2? */
 
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)      __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
-#define OMAP_DMA_CICR_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
-#define OMAP_DMA_CSR_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
-#define OMAP_DMA_CSDP_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
-#define OMAP_DMA_CEN_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
-#define OMAP_DMA_CFN_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
-#define OMAP_DMA_CSEI_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
-#define OMAP_DMA_CSFI_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDEI_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
-#define OMAP_DMA_CDFI_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
-#define OMAP_DMA_CSAC_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
-#define OMAP_DMA_CDAC_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
+#define OMAP_DMA_CCR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA_CLNK_CTRL_REG(n)      __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA_CICR_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA_CSR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA_CSDP_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA_CEN_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA_CFN_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA_CSEI_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA_CSFI_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA_CDEI_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA_CDFI_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA_CSAC_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA_CDAC_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
 
 #endif
 
@@ -113,11 +113,11 @@
 #define OMAP1_DMA_LCH_CTRL_REG(n)      __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
 
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)         __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
+#define OMAP2_DMA_CSSA_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
+#define OMAP2_DMA_CDSA_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
+#define OMAP2_DMA_CCEN_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
+#define OMAP2_DMA_CCFN_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
+#define OMAP2_DMA_COLOR_REG(n)         __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
 
 /*----------------------------------------------------------------------------*/
 

diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 675b78fdcc258b25bf32150e9085b3a6675f6f56..af3a32c90e7e134a141e9ef1b87fef96236662ce 100644 (file)
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -35,6 +35,7 @@
 #define L4_24XX_BASE           0x48000000
 #define L4_WK_243X_BASE                0x49000000
 #define L3_24XX_BASE           0x68000000
+#define L4_OMAP_BASE           L4_24XX_BASE
 
 /* interrupt controller */
 #define OMAP24XX_IC_BASE       (L4_24XX_BASE + 0xfe000)