#define AR5K_RESET_CTL_MAC     0x00000004      /* MAC reset (PCU+Baseband ?) [5210] */
 #define AR5K_RESET_CTL_PHY     0x00000008      /* PHY reset [5210] */
 #define AR5K_RESET_CTL_PCI     0x00000010      /* PCI Core reset (interrupts etc) */
-#define AR5K_RESET_CTL_CHIP    (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA |      \
-                               AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY)
 
 /*
  * Sleep control register
 
        udelay(15);
 
        if (ah->ah_version == AR5K_AR5210) {
-               val &= AR5K_RESET_CTL_CHIP;
-               mask &= AR5K_RESET_CTL_CHIP;
+               val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
+                       | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
+               mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
+                       | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
        } else {
                val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
                mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
 
        /* Reset chipset */
-       ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-               AR5K_RESET_CTL_BASEBAND | bus_flags);
+       if (ah->ah_version == AR5K_AR5210) {
+               ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                       AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
+                       AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
+                       mdelay(2);
+       } else {
+               ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                       AR5K_RESET_CTL_BASEBAND | bus_flags);
+       }
        if (ret) {
                ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
                return -EIO;
        }
 
-       if (ah->ah_version == AR5K_AR5210)
-               udelay(2300);
-
        /* ...wakeup again!*/
        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
        if (ret) {