}
        }
 }
+
+int pci_enable_resources(struct pci_dev *dev, int mask)
+{
+       u16 cmd, old_cmd;
+       int i;
+       struct resource *r;
+
+       pci_read_config_word(dev, PCI_COMMAND, &cmd);
+       old_cmd = cmd;
+
+       for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+               if (!(mask & (1 << i)))
+                       continue;
+
+               r = &dev->resource[i];
+
+               if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
+                       continue;
+               if ((i == PCI_ROM_RESOURCE) &&
+                               (!(r->flags & IORESOURCE_ROM_ENABLE)))
+                       continue;
+
+               if (!r->parent) {
+                       dev_err(&dev->dev, "device not available because of "
+                               "BAR %d [%llx:%llx] collisions\n", i,
+                               (unsigned long long) r->start,
+                               (unsigned long long) r->end);
+                       return -EINVAL;
+               }
+
+               if (r->flags & IORESOURCE_IO)
+                       cmd |= PCI_COMMAND_IO;
+               if (r->flags & IORESOURCE_MEM)
+                       cmd |= PCI_COMMAND_MEMORY;
+       }
+
+       if (cmd != old_cmd) {
+               dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
+                        old_cmd, cmd);
+               pci_write_config_word(dev, PCI_COMMAND, cmd);
+       }
+       return 0;
+}
 
 void pci_assign_unassigned_resources(void);
 void pdev_enable_device(struct pci_dev *);
 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
+int pci_enable_resources(struct pci_dev *, int mask);
 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
                    int (*)(struct pci_dev *, u8, u8));
 #define HAVE_PCI_REQ_REGIONS   2