]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/commitdiff
[MIPS] Fix warning by moving do_default_vi into CONFIG_CPU_MIPSR2_SRS
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Mon, 21 May 2007 14:45:38 +0000 (23:45 +0900)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 6 Jun 2007 18:34:33 +0000 (19:34 +0100)
This fixes the warning:

arch/mips/kernel/traps.c:931: warning: 'do_default_vi' defined but not used

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/traps.c

index 200de027f354ec8e0bb0919ab707f0ff4e640af1..3f58b6ac135815fe5944d3f98ec943f1529ce41d 100644 (file)
@@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs)
              (regs->cp0_cause & 0x7f) >> 2);
 }
 
-static asmlinkage void do_default_vi(void)
-{
-       show_regs(get_irq_regs());
-       panic("Caught unexpected vectored interrupt.");
-}
-
 /*
  * Some MIPS CPUs can enable/disable for cache parity detection, but do
  * it different ways.
@@ -1128,6 +1122,12 @@ void mips_srs_free(int set)
        clear_bit(set, &sr->sr_allocated);
 }
 
+static asmlinkage void do_default_vi(void)
+{
+       show_regs(get_irq_regs());
+       panic("Caught unexpected vectored interrupt.");
+}
+
 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 {
        unsigned long handler;