{
        struct NCR_700_Host_Parameters *hostdata = 
                (struct NCR_700_Host_Parameters *)host->hostdata[0];
-       __u32 dcntl_extra = 0;
        __u8 min_period;
        __u8 min_xferp = (hostdata->chip710 ? NCR_710_MIN_XFERP : NCR_700_MIN_XFERP);
 
                                burst_disable = BURST_DISABLE;
                                break;
                }
-               dcntl_extra = COMPAT_700_MODE;
+               hostdata->dcntl_extra |= COMPAT_700_MODE;
 
-               NCR_700_writeb(dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(hostdata->dcntl_extra, host, DCNTL_REG);
                NCR_700_writeb(burst_length | hostdata->dmode_extra,
                               host, DMODE_710_REG);
-               NCR_700_writeb(burst_disable | (hostdata->differential ? 
-                                               DIFF : 0), host, CTEST7_REG);
+               NCR_700_writeb(burst_disable | hostdata->ctest7_extra |
+                              (hostdata->differential ? DIFF : 0),
+                              host, CTEST7_REG);
                NCR_700_writeb(BTB_TIMER_DISABLE, host, CTEST0_REG);
                NCR_700_writeb(FULL_ARBITRATION | ENABLE_PARITY | PARITY
                               | AUTO_ATN, host, SCNTL0_REG);
                 * of spec: sync divider 2, async divider 3 */
                DEBUG(("53c700: sync 2 async 3\n"));
                NCR_700_writeb(SYNC_DIV_2_0, host, SBCL_REG);
-               NCR_700_writeb(ASYNC_DIV_3_0 | dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(ASYNC_DIV_3_0 | hostdata->dcntl_extra, host, DCNTL_REG);
                hostdata->sync_clock = hostdata->clock/2;
        } else  if(hostdata->clock > 50  && hostdata->clock <= 75) {
                /* sync divider 1.5, async divider 3 */
                DEBUG(("53c700: sync 1.5 async 3\n"));
                NCR_700_writeb(SYNC_DIV_1_5, host, SBCL_REG);
-               NCR_700_writeb(ASYNC_DIV_3_0 | dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(ASYNC_DIV_3_0 | hostdata->dcntl_extra, host, DCNTL_REG);
                hostdata->sync_clock = hostdata->clock*2;
                hostdata->sync_clock /= 3;
                
                /* sync divider 1, async divider 2 */
                DEBUG(("53c700: sync 1 async 2\n"));
                NCR_700_writeb(SYNC_DIV_1_0, host, SBCL_REG);
-               NCR_700_writeb(ASYNC_DIV_2_0 | dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(ASYNC_DIV_2_0 | hostdata->dcntl_extra, host, DCNTL_REG);
                hostdata->sync_clock = hostdata->clock;
        } else if(hostdata->clock > 25 && hostdata->clock <=37) {
                /* sync divider 1, async divider 1.5 */
                DEBUG(("53c700: sync 1 async 1.5\n"));
                NCR_700_writeb(SYNC_DIV_1_0, host, SBCL_REG);
-               NCR_700_writeb(ASYNC_DIV_1_5 | dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(ASYNC_DIV_1_5 | hostdata->dcntl_extra, host, DCNTL_REG);
                hostdata->sync_clock = hostdata->clock;
        } else {
                DEBUG(("53c700: sync 1 async 1\n"));
                NCR_700_writeb(SYNC_DIV_1_0, host, SBCL_REG);
-               NCR_700_writeb(ASYNC_DIV_1_0 | dcntl_extra, host, DCNTL_REG);
+               NCR_700_writeb(ASYNC_DIV_1_0 | hostdata->dcntl_extra, host, DCNTL_REG);
                /* sync divider 1, async divider 1 */
                hostdata->sync_clock = hostdata->clock;
        }
 
        __u8    state;
        #define NCR_700_FLAG_AUTOSENSE  0x01
        __u8    flags;
+       __u8    pad1[2];        /* Needed for m68k where min alignment is 2 bytes */
        int     tag;
        __u32   resume_offset;
        struct scsi_cmnd *cmnd;
        void __iomem    *base;          /* the base for the port (copied to host) */
        struct device   *dev;
        __u32   dmode_extra;    /* adjustable bus settings */
+       __u32   dcntl_extra;    /* adjustable bus settings */
+       __u32   ctest7_extra;   /* adjustable bus settings */
        __u32   differential:1; /* if we are differential */
 #ifdef CONFIG_53C700_LE_ON_BE
        /* This option is for HP only.  Set it if your chip is wired for
 #define                SEL_TIMEOUT_DISABLE     0x10 /* 710 only */
 #define         DFP                     0x08
 #define         EVP                     0x04
+#define         CTEST7_TT1              0x02
 #define                DIFF                    0x01
 #define CTEST6_REG                      0x1A
 #define        TEMP_REG                        0x1C
 #define                SOFTWARE_RESET          0x01
 #define                COMPAT_700_MODE         0x01
 #define        SCRPTS_16BITS           0x20
+#define                EA_710                  0x20
 #define                ASYNC_DIV_2_0           0x00
 #define                ASYNC_DIV_1_5           0x40
 #define                ASYNC_DIV_1_0           0x80