case XFER_SW_DMA_0:
                cycle_time = 480;
                break;
-       default:
-               return;
        }
 
        /*
 
                        strobe = ATA_DMA2_STROBE;
                        hold = ATA_DMA2_HOLD;
                        break;
-               default:
-                       return;
        }
 
        if (speed >= XFER_UDMA_0)
 
         * case could happen iff the transfer mode has already been set on
         * the device by ide-proc.c::set_xfer_rate()).
         */
+       if (rate < XFER_PIO_0) {
+               if (hwif->host_flags & IDE_HFLAG_ABUSE_SET_DMA_MODE)
+                       return ide_set_dma_mode(drive, rate);
+               else
+                       return ide_config_drive_speed(drive, rate);
+       }
 
        return ide_set_dma_mode(drive, rate);
 }
 
 
                break;
 #endif
-       default:
-               return;
        }
 
        au_writel(mem_sttime,MEM_STTIME2);
 
                .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
                .host_flags     = IDE_HFLAG_SERIALIZE |
                                  IDE_HFLAG_NO_ATAPI_DMA |
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE |
                                  IDE_HFLAG_OFF_BOARD,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .init_chipset   = init_chipset_aec62xx,
                .init_hwif      = init_hwif_aec62xx,
                .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE |
                                  IDE_HFLAG_OFF_BOARD,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .init_chipset   = init_chipset_aec62xx,
                .init_hwif      = init_hwif_aec62xx,
                .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA,
+               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA4,
                .name           = "AEC6280",
                .init_chipset   = init_chipset_aec62xx,
                .init_hwif      = init_hwif_aec62xx,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE |
+                                 IDE_HFLAG_OFF_BOARD,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
                .init_chipset   = init_chipset_aec62xx,
                .init_hwif      = init_hwif_aec62xx,
                .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE |
+                                 IDE_HFLAG_OFF_BOARD,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
 
        u8 tmpbyte              = 0x00;
        int m5229_udma          = (hwif->channel) ? 0x57 : 0x56;
 
-       if (speed < XFER_PIO_0)
-               return;
-
        if (speed == XFER_UDMA_6)
                speed1 = 0x47;
 
 
 #define IDE_HFLAGS_AMD \
        (IDE_HFLAG_PIO_NO_BLACKLIST | \
         IDE_HFLAG_PIO_NO_DOWNGRADE | \
+        IDE_HFLAG_ABUSE_SET_DMA_MODE | \
         IDE_HFLAG_POST_SET_MODE | \
         IDE_HFLAG_IO_32BIT | \
         IDE_HFLAG_UNMASK_IRQS | \
 
        u32 tmp32;
        u16 tmp16;
 
-       if (speed < XFER_MW_DMA_0)
-               return;
-
        spin_lock_irqsave(&atiixp_lock, flags);
 
        save_mdma_mode[drive->dn] = 0;
 
        case XFER_MW_DMA_0:
                program_cycle_times(drive, 480, 215);
                break;
-       default:
-               return;
        }
 
        if (speed >= XFER_SW_DMA_0)
 
                                  IDE_HFLAG_CS5520 |            \
                                  IDE_HFLAG_VDMA |              \
                                  IDE_HFLAG_NO_ATAPI_DMA |      \
+                                 IDE_HFLAG_ABUSE_SET_DMA_MODE |\
                                  IDE_HFLAG_BOOTABLE,           \
                .pio_mask       = ATA_PIO4,                     \
        }
 
                case XFER_MW_DMA_0:     timings = 0x00077771; break;
                case XFER_MW_DMA_1:     timings = 0x00012121; break;
                case XFER_MW_DMA_2:     timings = 0x00002020; break;
-               default:
-                       return;
        }
        basereg = CS5530_BASEREG(drive->hwif);
        reg = inl(basereg + 4);                 /* get drive0 config register */
 
        .name           = "CS5535",
        .init_hwif      = init_hwif_cs5535,
        .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
-                         IDE_HFLAG_BOOTABLE,
+                         IDE_HFLAG_ABUSE_SET_DMA_MODE | IDE_HFLAG_BOOTABLE,
        .pio_mask       = ATA_PIO4,
        .mwdma_mask     = ATA_MWDMA2,
        .udma_mask      = ATA_UDMA4,
 
        hwif->set_dma_mode = &hpt34x_set_mode;
 }
 
+#define IDE_HFLAGS_HPT34X \
+       (IDE_HFLAG_NO_ATAPI_DMA | \
+        IDE_HFLAG_ABUSE_SET_DMA_MODE | \
+        IDE_HFLAG_NO_AUTODMA)
+
 static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
        { /* 0 */
                .name           = "HPT343",
                .init_chipset   = init_chipset_hpt34x,
                .init_hwif      = init_hwif_hpt34x,
                .extra          = 16,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
-                                 IDE_HFLAG_NO_AUTODMA,
+               .host_flags     = IDE_HFLAGS_HPT34X,
                .pio_mask       = ATA_PIO5,
        },
        { /* 1 */
                .init_chipset   = init_chipset_hpt34x,
                .init_hwif      = init_hwif_hpt34x,
                .extra          = 16,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA |
-                                 IDE_HFLAG_NO_AUTODMA |
-                                 IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
                .pio_mask       = ATA_PIO5,
 #ifdef CONFIG_HPT34X_AUTODMA
                .swdma_mask     = ATA_SWDMA2,
 
        return 0;
 }
 
+#define IDE_HFLAGS_HPT3XX \
+       (IDE_HFLAG_NO_ATAPI_DMA | \
+        IDE_HFLAG_ABUSE_SET_DMA_MODE | \
+        IDE_HFLAG_OFF_BOARD)
+
 static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
        {       /* 0 */
                .name           = "HPT36x",
                 */
                .enablebits     = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_SINGLE |
-                                 IDE_HFLAG_NO_ATAPI_DMA |
-                                 IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        },{     /* 1 */
                .init_dma       = init_dma_hpt366,
                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        },{     /* 2 */
                .init_dma       = init_dma_hpt366,
                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        },{     /* 3 */
                .init_dma       = init_dma_hpt366,
                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        },{     /* 4 */
                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
                .udma_mask      = ATA_UDMA5,
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        },{     /* 5 */
                .init_dma       = init_dma_hpt366,
                .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
                .extra          = 240,
-               .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_HPT3XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
        }
 
        pci_read_config_byte(dev, 0x54, ®54);
        pci_read_config_byte(dev, 0x55, ®55);
 
-       switch(speed) {
-               case XFER_UDMA_6:
-               case XFER_UDMA_4:
-               case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
-               case XFER_UDMA_5:
-               case XFER_UDMA_3:
-               case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
-               case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
-                       break;
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_SW_DMA_2:
-                       break;
-               default:
-                       return;
-       }
-
        if (speed >= XFER_UDMA_0) {
+               u8 udma = speed - XFER_UDMA_0;
+
+               u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
+
                if (!(reg48 & u_flag))
                        pci_write_config_byte(dev, 0x48, reg48 | u_flag);
                if (speed >= XFER_UDMA_5) {
 
        if (max_dma_rate(hwif->pci_dev) == 4) {
                u8 mode = speed & 0x07;
 
-               switch (speed) {
-                       case XFER_UDMA_6:
-                       case XFER_UDMA_5:
-                       case XFER_UDMA_4:
-                       case XFER_UDMA_3:
-                       case XFER_UDMA_2:
-                       case XFER_UDMA_1:
-                       case XFER_UDMA_0:
-                               set_indexed_reg(hwif, 0x10 + adj,
-                                               udma_timings[mode].reg10);
-                               set_indexed_reg(hwif, 0x11 + adj,
-                                               udma_timings[mode].reg11);
-                               set_indexed_reg(hwif, 0x12 + adj,
-                                               udma_timings[mode].reg12);
-                               break;
-                       case XFER_MW_DMA_2:
-                       case XFER_MW_DMA_1:
-                       case XFER_MW_DMA_0:
-                               set_indexed_reg(hwif, 0x0e + adj,
-                                               mwdma_timings[mode].reg0e);
-                               set_indexed_reg(hwif, 0x0f + adj,
-                                               mwdma_timings[mode].reg0f);
-                               break;
-                       default:
-                               printk(KERN_ERR "pdc202xx_new: "
-                                      "Unknown speed %d ignored\n", speed);
+               if (speed >= XFER_UDMA_0) {
+                       set_indexed_reg(hwif, 0x10 + adj,
+                                       udma_timings[mode].reg10);
+                       set_indexed_reg(hwif, 0x11 + adj,
+                                       udma_timings[mode].reg11);
+                       set_indexed_reg(hwif, 0x12 + adj,
+                                       udma_timings[mode].reg12);
+               } else {
+                       set_indexed_reg(hwif, 0x0e + adj,
+                                       mwdma_timings[mode].reg0e);
+                       set_indexed_reg(hwif, 0x0f + adj,
+                                       mwdma_timings[mode].reg0f);
                }
        } else if (speed == XFER_UDMA_2) {
                /* Set tHOLD bit to 0 if using UDMA mode 2 */
 
        }
 }
 
+#define IDE_HFLAGS_PDC202XX \
+       (IDE_HFLAG_ERROR_STOPS_FIFO | \
+        IDE_HFLAG_ABUSE_SET_DMA_MODE | \
+        IDE_HFLAG_OFF_BOARD)
+
 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
        { \
                .name           = name_str, \
                .init_hwif      = init_hwif_pdc202xx, \
                .init_dma       = init_dma_pdc202xx, \
                .extra          = 48, \
-               .host_flags     = IDE_HFLAG_ERROR_STOPS_FIFO | \
-                                 extra_flags | \
-                                 IDE_HFLAG_OFF_BOARD, \
+               .host_flags     = IDE_HFLAGS_PDC202XX | extra_flags, \
                .pio_mask       = ATA_PIO4, \
                .mwdma_mask     = ATA_MWDMA2, \
                .udma_mask      = udma, \
                .init_hwif      = init_hwif_pdc202xx,
                .init_dma       = init_dma_pdc202xx,
                .extra          = 16,
-               .host_flags     = IDE_HFLAG_ERROR_STOPS_FIFO |
-                                 IDE_HFLAG_OFF_BOARD,
+               .host_flags     = IDE_HFLAGS_PDC202XX,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA2,
 
        pci_read_config_byte(dev, 0x54, ®54);
        pci_read_config_byte(dev, 0x55, ®55);
 
-       switch(speed) {
-               case XFER_UDMA_4:
-               case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
-               case XFER_UDMA_5:
-               case XFER_UDMA_3:
-               case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
-               case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_SW_DMA_2:     break;
-               default:                return;
-       }
-
        if (speed >= XFER_UDMA_0) {
+               u8 udma = speed - XFER_UDMA_0;
+
+               u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
+
                if (!(reg48 & u_flag))
                        pci_write_config_byte(dev, 0x48, reg48 | u_flag);
                if (speed == XFER_UDMA_5) {
 
                                case PCI_CLK_66:        timings = 0x00015151;   break;
                        }
                        break;
-               default:
-                       return;
        }
 
        if (unit == 0) {                        /* are we configuring drive0? */
 
                offset = 0; /* 100MHz */
        }
 
-       switch (speed) {
-       case XFER_UDMA_6:
-       case XFER_UDMA_5:
-       case XFER_UDMA_4:
-       case XFER_UDMA_3:
-       case XFER_UDMA_2:
-       case XFER_UDMA_1:
-       case XFER_UDMA_0:
-               idx = speed - XFER_UDMA_0;
-               break;
-       default:
-               return;
-       }
+       idx = speed - XFER_UDMA_0;
 
        jcactsel = JCACTSELtbl[offset][idx];
        if (is_slave) {
 
        }
 }
 
+#define IDE_HFLAGS_SVWKS \
+       (IDE_HFLAG_LEGACY_IRQS | \
+        IDE_HFLAG_ABUSE_SET_DMA_MODE | \
+        IDE_HFLAG_BOOTABLE)
+
 static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
        {       /* 0 */
                .name           = "SvrWks OSB4",
                .init_chipset   = init_chipset_svwks,
                .init_hwif      = init_hwif_svwks,
-               .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
+               .host_flags     = IDE_HFLAGS_SVWKS,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
                .name           = "SvrWks CSB5",
                .init_chipset   = init_chipset_svwks,
                .init_hwif      = init_hwif_svwks,
-               .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
+               .host_flags     = IDE_HFLAGS_SVWKS,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
                .name           = "SvrWks CSB6",
                .init_chipset   = init_chipset_svwks,
                .init_hwif      = init_hwif_svwks,
-               .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
+               .host_flags     = IDE_HFLAGS_SVWKS,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
                .name           = "SvrWks CSB6",
                .init_chipset   = init_chipset_svwks,
                .init_hwif      = init_hwif_svwks,
-               .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
-                                 IDE_HFLAG_BOOTABLE,
+               .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
                .name           = "SvrWks HT1000",
                .init_chipset   = init_chipset_svwks,
                .init_hwif      = init_hwif_svwks,
-               .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE |
-                                 IDE_HFLAG_BOOTABLE,
+               .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
                .pio_mask       = ATA_PIO4,
                .mwdma_mask     = ATA_MWDMA2,
                .udma_mask      = ATA_UDMA5,
 
 
        scsc = is_sata(hwif) ? 1 : scsc;
 
-       switch(speed) {
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_MW_DMA_0:
-                       multi = dma[speed - XFER_MW_DMA_0];
-                       mode |= ((unit) ? 0x20 : 0x02);
-                       break;
-               case XFER_UDMA_6:
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-                       multi = dma[2];
-                       ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
-                                          (ultra5[speed - XFER_UDMA_0]));
-                       mode |= ((unit) ? 0x30 : 0x03);
-                       break;
-               default:
-                       return;
+       if (speed >= XFER_UDMA_0) {
+               multi = dma[2];
+               ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
+                                ultra5[speed - XFER_UDMA_0]);
+               mode |= (unit ? 0x30 : 0x03);
+       } else {
+               multi = dma[speed - XFER_MW_DMA_0];
+               mode |= (unit ? 0x20 : 0x02);
        }
 
        if (hwif->mmio) {
 
 
 static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
 {
-       /* Config chip for mode */
-       switch(speed) {
-               case XFER_UDMA_6:
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-                       sis_program_udma_timings(drive, speed);
-                       break;
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_MW_DMA_0:
-                       sis_program_timings(drive, speed);
-                       break;
-               default:
-                       break;
-       }
+       if (speed >= XFER_UDMA_0)
+               sis_program_udma_timings(drive, speed);
+       else
+               sis_program_timings(drive, speed);
 }
 
 static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
 
        DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
             drive->name, ide_xfer_verbose(speed)));
 
-       switch (speed) {
-       case XFER_MW_DMA_2:
-       case XFER_MW_DMA_1:
-       case XFER_MW_DMA_0:
-               drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
+       drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
 
-               /*
-                * Store the DMA timings so that we can actually program
-                * them when DMA will be turned on...
-                */
-               drive->drive_data &= 0x0000ffff;
-               drive->drive_data |= (unsigned long)drv_ctrl << 16;
+       /*
+        * Store the DMA timings so that we can actually program
+        * them when DMA will be turned on...
+        */
+       drive->drive_data &= 0x0000ffff;
+       drive->drive_data |= (unsigned long)drv_ctrl << 16;
 
-               /*
-                * If we are already using DMA, we just reprogram
-                * the drive control register.
-                */
-               if (drive->using_dma) {
-                       struct pci_dev *dev     = HWIF(drive)->pci_dev;
-                       int reg                 = 0x44 + drive->dn * 4;
-
-                       pci_write_config_word(dev, reg, drv_ctrl);
-               }
-               break;
-       default:
-               return;
+       /*
+        * If we are already using DMA, we just reprogram
+        * the drive control register.
+        */
+       if (drive->using_dma) {
+               struct pci_dev *dev     = HWIF(drive)->pci_dev;
+               int reg                 = 0x44 + drive->dn * 4;
+
+               pci_write_config_word(dev, reg, drv_ctrl);
        }
 }
 
 
        pci_read_config_word(dev, 0x48, ®48);
        pci_read_config_word(dev, 0x4a, ®4a);
 
-       switch(speed) {
-               case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
-               case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
-               case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
-               case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
-               case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_SW_DMA_2:     break;
-               default:                return;
-       }
-
        if (speed >= XFER_UDMA_0) {
+               u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
+
                if (!(reg48 & u_flag))
                        pci_write_config_word(dev, 0x48, reg48|u_flag);
                /* FIXME: (reg4a & a_speed) ? */
 
        .name           = "TC86C001",
        .init_chipset   = init_chipset_tc86c001,
        .init_hwif      = init_hwif_tc86c001,
-       .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD,
+       .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD |
+                         IDE_HFLAG_ABUSE_SET_DMA_MODE,
        .pio_mask       = ATA_PIO4,
        .mwdma_mask     = ATA_MWDMA2,
        .udma_mask      = ATA_UDMA4,
 
                case XFER_PIO_0:
                        timing = 0x0808;
                        break;
-               default:
-                       return;
        }
 
        triflex_timings &= ~(0xFFFF << (16 * unit));
 
        .enablebits     = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
        .host_flags     = IDE_HFLAG_PIO_NO_BLACKLIST |
                          IDE_HFLAG_PIO_NO_DOWNGRADE |
+                         IDE_HFLAG_ABUSE_SET_DMA_MODE |
                          IDE_HFLAG_POST_SET_MODE |
                          IDE_HFLAG_IO_32BIT |
                          IDE_HFLAG_BOOTABLE,
 
        tl[0] = *timings;
        tl[1] = *timings2;
 
-       switch(speed) {
 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
-               case XFER_UDMA_6:
-               case XFER_UDMA_5:
-               case XFER_UDMA_4:
-               case XFER_UDMA_3:
-               case XFER_UDMA_2:
-               case XFER_UDMA_1:
-               case XFER_UDMA_0:
-                       if (pmif->kind == controller_kl_ata4)
-                               ret = set_timings_udma_ata4(&tl[0], speed);
-                       else if (pmif->kind == controller_un_ata6
-                                || pmif->kind == controller_k2_ata6)
-                               ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
-                       else if (pmif->kind == controller_sh_ata6)
-                               ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
-                       else
-                               ret = 1;
-                       break;
-               case XFER_MW_DMA_2:
-               case XFER_MW_DMA_1:
-               case XFER_MW_DMA_0:
-                       set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
-                       break;
-               case XFER_SW_DMA_2:
-               case XFER_SW_DMA_1:
-               case XFER_SW_DMA_0:
-                       return;
+       if (speed >= XFER_UDMA_0) {
+               if (pmif->kind == controller_kl_ata4)
+                       ret = set_timings_udma_ata4(&tl[0], speed);
+               else if (pmif->kind == controller_un_ata6
+                        || pmif->kind == controller_k2_ata6)
+                       ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
+               else if (pmif->kind == controller_sh_ata6)
+                       ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
+               else
+                       ret = -1;
+       } else
+               set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
-               default:
-                       ret = 1;
-       }
        if (ret)
                return;
 
 
        IDE_HFLAG_IO_32BIT              = (1 << 24),
        /* unmask IRQs */
        IDE_HFLAG_UNMASK_IRQS           = (1 << 25),
+       IDE_HFLAG_ABUSE_SET_DMA_MODE    = (1 << 26),
 };
 
 #ifdef CONFIG_BLK_DEV_OFFBOARD