ASoC: TWL4030: Syncronize the reg_cache for ANAMICL after the offset cancelation

The offset cancelation bit in ANAMICL register is self cleanig.
Make sure that the reg_cache holds the same value as the HW
register.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 796f34cac85d01d8298a2eba785997e72ad7c1fe..24419afd319eae5c72ec2a37fb0b48ce7cce47c5 100644 (file)
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -913,6 +913,9 @@ static void twl4030_power_up(struct snd_soc_codec *codec)
                 ((byte & TWL4030_CNCL_OFFSET_START) ==
                  TWL4030_CNCL_OFFSET_START));
 
+       /* Make sure that the reg_cache has the same value as the HW */
+       twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
+
        /* anti-pop when changing analog gain */
        regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
        twl4030_write(codec, TWL4030_REG_MISC_SET_1,