struct iwl3945_tx_queue txq[IWL_MAX_NUM_QUEUES];
 
        unsigned long status;
-       u32 config;
 
        int last_rx_rssi;       /* From Rx packet statisitics */
        int last_rx_noise;      /* From beacon statistics */
 
        u32 scd_base_addr;      /* scheduler sram base address */
 
        unsigned long status;
-       u32 config;
 
        int last_rx_rssi;       /* From Rx packet statisitics */
        int last_rx_noise;      /* From beacon statistics */
 
 
        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
                IWL_ERROR("Start IWL Error Log Dump:\n");
-               IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
-                         priv->status, priv->config, count);
+               IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
        }
 
        IWL_ERROR("Desc       Time       asrtPC  blink2 "
 
 
        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
                IWL_ERROR("Start IWL Error Log Dump:\n");
-               IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
-                         priv->status, priv->config, count);
+               IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
        }
 
        desc = iwl4965_read_targ_mem(priv, base + 1 * sizeof(u32));