* private backbuffer/depthbuffer usage.
         */
        dev_priv->use_mi_batchbuffer_start = 0;
+       if (IS_I965G(dev)) /* 965 doesn't support older method */
+               dev_priv->use_mi_batchbuffer_start = 1;
 
        /* Allow hardware batchbuffers unless told otherwise.
         */
 
                if (dev_priv->use_mi_batchbuffer_start) {
                        BEGIN_LP_RING(2);
-                       OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
-                       OUT_RING(batch->start | MI_BATCH_NON_SECURE);
+                       if (IS_I965G(dev)) {
+                               OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
+                               OUT_RING(batch->start);
+                       } else {
+                               OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
+                               OUT_RING(batch->start | MI_BATCH_NON_SECURE);
+                       }
                        ADVANCE_LP_RING();
                } else {
                        BEGIN_LP_RING(4);
 
        switch (param.param) {
        case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
-               dev_priv->use_mi_batchbuffer_start = param.value;
+               if (!IS_I965G(dev))
+                       dev_priv->use_mi_batchbuffer_start = param.value;
                break;
        case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
                dev_priv->tex_lru_log_granularity = param.value;
 
 #define MI_BATCH_BUFFER_START  (0x31<<23)
 #define MI_BATCH_BUFFER_END    (0xA<<23)
 #define MI_BATCH_NON_SECURE    (1)
+#define MI_BATCH_NON_SECURE_I965 (1<<8)
 
 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)