.start  = GE00_PHYS_BASE + 0x2000,
                .end    = GE00_PHYS_BASE + 0x3fff,
                .flags  = IORESOURCE_MEM,
+       }, {
+               .name   = "ge err irq",
+               .start  = IRQ_MV78XX0_GE_ERR,
+               .end    = IRQ_MV78XX0_GE_ERR,
+               .flags  = IORESOURCE_IRQ,
        },
 };
 
        .dev            = {
                .platform_data  = &mv78xx0_ge00_shared_data,
        },
-       .num_resources  = 1,
+       .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
        .resource       = mv78xx0_ge00_shared_resources,
 };
 
 
        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
        mov     \irqnr, #31
        ands    \irqstat, \irqstat, \tmp
+       bne     1001f
 
        @ if no low interrupts set, check high interrupts
-       ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-       ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-       moveq   \irqnr, #63
-       andeqs  \irqstat, \irqstat, \tmp
+       ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+       ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+       mov     \irqnr, #63
+       ands    \irqstat, \irqstat, \tmp
+       bne     1001f
+
+       @ if no high interrupts set, check error interrupts
+       ldr     \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
+       ldr     \tmp, [\base, #IRQ_MASK_ERR_OFF]
+       mov     \irqnr, #95
+       ands    \irqstat, \irqstat, \tmp
 
        @ find first active interrupt source
-       clzne   \irqstat, \irqstat
+1001:  clzne   \irqstat, \irqstat
        subne   \irqnr, \irqnr, \irqstat
        .endm
 
 #define IRQ_MV78XX0_DB_IN      60
 #define IRQ_MV78XX0_DB_OUT     61
 
+/*
+ * MV78xx0 Error Interrupt Controller
+ */
+#define IRQ_MV78XX0_GE_ERR     70
+
 /*
  * MV78XX0 General Purpose Pins
  */
-#define IRQ_MV78XX0_GPIO_START 64
+#define IRQ_MV78XX0_GPIO_START 96
 #define NR_GPIO_IRQS           GPIO_MAX
 
 #define NR_IRQS                        (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
 
 #define   BRIDGE_INT_TIMER1    0x0004
 #define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
 #define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_ERR_OFF    0x0000
 #define   IRQ_CAUSE_LOW_OFF    0x0004
 #define   IRQ_CAUSE_HIGH_OFF   0x0008
+#define   IRQ_MASK_ERR_OFF     0x000c
 #define   IRQ_MASK_LOW_OFF     0x0010
 #define   IRQ_MASK_HIGH_OFF    0x0014
 #define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
 
 {
        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+       orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
 }