stat = spu_int_stat_get(spu, 0) & mask;
 
        spu->class_0_pending |= stat;
-       spu->class_0_dsisr = spu_mfc_dsisr_get(spu);
        spu->class_0_dar = spu_mfc_dar_get(spu);
        spin_unlock(&spu->register_lock);
 
        spu->stop_callback(spu, 0);
 
        spu->class_0_pending = 0;
-       spu->class_0_dsisr = 0;
        spu->class_0_dar = 0;
 
        spu_int_stat_clear(spu, 0, stat);
 
                switch(irq) {
                case 0 :
                        ctx->csa.class_0_pending = spu->class_0_pending;
-                       ctx->csa.class_0_dsisr = spu->class_0_dsisr;
                        ctx->csa.class_0_dar = spu->class_0_dar;
                        break;
                case 1 :
        if (test_bit(SPU_SCHED_NOTIFY_ACTIVE, &ctx->sched_flags))
                return 1;
 
-       dsisr = ctx->csa.class_0_dsisr;
-       if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
-               return 1;
-
        dsisr = ctx->csa.class_1_dsisr;
        if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
                return 1;
 
        DUMP_FIELD(spu, "0x%lx", flags);
        DUMP_FIELD(spu, "%d", class_0_pending);
        DUMP_FIELD(spu, "0x%lx", class_0_dar);
-       DUMP_FIELD(spu, "0x%lx", class_0_dsisr);
        DUMP_FIELD(spu, "0x%lx", class_1_dar);
        DUMP_FIELD(spu, "0x%lx", class_1_dsisr);
        DUMP_FIELD(spu, "0x%lx", irqs[0]);
 
        u64 flags;
        u64 class_0_pending;
        u64 class_0_dar;
-       u64 class_0_dsisr;
        u64 class_1_dar;
        u64 class_1_dsisr;
        size_t ls_size;
 
        u64 spu_chnldata_RW[32];
        u32 spu_mailbox_data[4];
        u32 pu_mailbox_data[1];
-       u64 class_0_dar, class_0_dsisr, class_0_pending;
+       u64 class_0_dar, class_0_pending;
        u64 class_1_dar, class_1_dsisr;
        unsigned long suspend_time;
        spinlock_t register_lock;