S: Supported
INPUT (KEYBOARD, MOUSE, JOYSTICK) DRIVERS
-P: Vojtech Pavlik
-M: vojtech@suse.cz
+P: Dmitry Torokhov
+M: dtor_core@ameritech.net
L: linux-input@atrey.karlin.mff.cuni.cz
L: linux-joystick@atrey.karlin.mff.cuni.cz
T: git kernel.org:/pub/scm/linux/kernel/git/dtor/input.git
#define CAT1(x,y) x##y
#define CAT(x,y) CAT1(x,y)
-#define DO_DEFAULT_RTC rtc_port: 0x70
+#define DO_DEFAULT_RTC .rtc_port = 0x70
#define DO_EV4_MMU \
.max_asn = EV4_MAX_ASN, \
break;
case R_ARM_PC24:
+ case R_ARM_CALL:
+ case R_ARM_JUMP24:
offset = (*(u32 *)loc & 0x00ffffff) << 2;
if (offset & 0x02000000)
offset -= 0x04000000;
PSPR = 0;
/* restore registers */
+ RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
+ RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
- RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
- RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
#ifdef CONFIG_PXA27x
RESTORE(MDREFR);
- RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3);
- RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
+ RESTORE_GPLEVEL(3); RESTORE(GPDR3);
+ RESTORE(GAFR3_L); RESTORE(GAFR3_U);
+ RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
RESTORE(PFER); RESTORE(PKWR);
#endif
if (cpu == 0)
return -EBUSY;
- /* We enable the timer again on the exit path of the death loop */
- disable_APIC_timer();
+ clear_local_APIC();
/* Allow any queued timer interrupts to get serviced */
local_irq_enable();
mdelay(1);
}
EXPORT_SYMBOL(ioremap_nocache);
+/**
+ * iounmap - Free a IO remapping
+ * @addr: virtual address from ioremap_*
+ *
+ * Caller must ensure there is only one unmapping for the same pointer.
+ */
void iounmap(volatile void __iomem *addr)
{
- struct vm_struct *p;
+ struct vm_struct *p, *o;
if ((void __force *)addr <= high_memory)
return;
addr < phys_to_virt(ISA_END_ADDRESS))
return;
- write_lock(&vmlist_lock);
- p = __remove_vm_area((void *)(PAGE_MASK & (unsigned long __force)addr));
- if (!p) {
- printk(KERN_WARNING "iounmap: bad address %p\n", addr);
+ addr = (volatile void __iomem *)(PAGE_MASK & (unsigned long __force)addr);
+
+ /* Use the vm area unlocked, assuming the caller
+ ensures there isn't another iounmap for the same address
+ in parallel. Reuse of the virtual address is prevented by
+ leaving it in the global lists until we're done with it.
+ cpa takes care of the direct mappings. */
+ read_lock(&vmlist_lock);
+ for (p = vmlist; p; p = p->next) {
+ if (p->addr == addr)
+ break;
+ }
+ read_unlock(&vmlist_lock);
+
+ if (!p) {
+ printk("iounmap: bad address %p\n", addr);
dump_stack();
- goto out_unlock;
+ return;
}
+ /* Reset the direct mapping. Can block */
if ((p->flags >> 20) && p->phys_addr < virt_to_phys(high_memory) - 1) {
change_page_attr(virt_to_page(__va(p->phys_addr)),
p->size >> PAGE_SHIFT,
PAGE_KERNEL);
global_flush_tlb();
}
-out_unlock:
- write_unlock(&vmlist_lock);
+
+ /* Finally remove it */
+ o = remove_vm_area((void *)addr);
+ BUG_ON(p != o || o == NULL);
kfree(p);
}
EXPORT_SYMBOL(iounmap);
#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
-static int pci_conf1_read(unsigned int seg, unsigned int bus,
+int pci_conf1_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
unsigned long flags;
return 0;
}
-static int pci_conf1_write(unsigned int seg, unsigned int bus,
+int pci_conf1_write(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 value)
{
unsigned long flags;
/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
+static DECLARE_BITMAP(fallback_slots, 32);
+
/*
* Functions for accessing PCI configuration space with MMCONFIG accesses
*/
-static u32 get_base_addr(unsigned int seg, int bus)
+static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
int cfg_num = -1;
struct acpi_table_mcfg_config *cfg;
+ if (seg == 0 && bus == 0 &&
+ test_bit(PCI_SLOT(devfn), fallback_slots))
+ return 0;
+
while (1) {
++cfg_num;
if (cfg_num >= pci_mmcfg_config_num) {
- /* something bad is going on, no cfg table is found. */
- /* so we fall back to the old way we used to do this */
- /* and just rely on the first entry to be correct. */
- return pci_mmcfg_config[0].base_address;
+ /* Not found - fallback to type 1 */
+ return 0;
}
cfg = &pci_mmcfg_config[cfg_num];
if (cfg->pci_segment_group_number != seg)
}
}
-static inline void pci_exp_set_dev_base(unsigned int seg, int bus, int devfn)
+static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
- u32 dev_base = get_base_addr(seg, bus) | (bus << 20) | (devfn << 12);
+ u32 dev_base = base | (bus << 20) | (devfn << 12);
if (dev_base != mmcfg_last_accessed_device) {
mmcfg_last_accessed_device = dev_base;
set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
unsigned int devfn, int reg, int len, u32 *value)
{
unsigned long flags;
+ u32 base;
if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL;
+ base = get_base_addr(seg, bus, devfn);
+ if (!base)
+ return pci_conf1_read(seg,bus,devfn,reg,len,value);
+
spin_lock_irqsave(&pci_config_lock, flags);
- pci_exp_set_dev_base(seg, bus, devfn);
+ pci_exp_set_dev_base(base, bus, devfn);
switch (len) {
case 1:
unsigned int devfn, int reg, int len, u32 value)
{
unsigned long flags;
+ u32 base;
if ((bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL;
+ base = get_base_addr(seg, bus, devfn);
+ if (!base)
+ return pci_conf1_write(seg,bus,devfn,reg,len,value);
+
spin_lock_irqsave(&pci_config_lock, flags);
- pci_exp_set_dev_base(seg, bus, devfn);
+ pci_exp_set_dev_base(base, bus, devfn);
switch (len) {
case 1:
.write = pci_mmcfg_write,
};
+/* K8 systems have some devices (typically in the builtin northbridge)
+ that are only accessible using type1
+ Normally this can be expressed in the MCFG by not listing them
+ and assigning suitable _SEGs, but this isn't implemented in some BIOS.
+ Instead try to discover all devices on bus 0 that are unreachable using MM
+ and fallback for them.
+ We only do this for bus 0/seg 0 */
+static __init void unreachable_devices(void)
+{
+ int i;
+ unsigned long flags;
+
+ for (i = 0; i < 32; i++) {
+ u32 val1;
+ u32 addr;
+
+ pci_conf1_read(0, 0, PCI_DEVFN(i, 0), 0, 4, &val1);
+ if (val1 == 0xffffffff)
+ continue;
+
+ /* Locking probably not needed, but safer */
+ spin_lock_irqsave(&pci_config_lock, flags);
+ addr = get_base_addr(0, 0, PCI_DEVFN(i, 0));
+ if (addr != 0)
+ pci_exp_set_dev_base(addr, 0, PCI_DEVFN(i, 0));
+ if (addr == 0 || readl((u32 __iomem *)mmcfg_virt_addr) != val1)
+ set_bit(i, fallback_slots);
+ spin_unlock_irqrestore(&pci_config_lock, flags);
+ }
+}
+
static int __init pci_mmcfg_init(void)
{
if ((pci_probe & PCI_PROBE_MMCONF) == 0)
raw_pci_ops = &pci_mmcfg;
pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
+ unreachable_devices();
+
out:
return 0;
}
extern int (*pcibios_enable_irq)(struct pci_dev *dev);
extern void (*pcibios_disable_irq)(struct pci_dev *dev);
+
+extern int pci_conf1_write(unsigned int seg, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 value);
+extern int pci_conf1_read(unsigned int seg, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *value);
+
+
/* drop floating-point and debug-register state if it exists: */
current->thread.flags &= ~(IA64_THREAD_FPH_VALID | IA64_THREAD_DBG_VALID);
ia64_drop_fpu(current);
+#ifdef CONFIG_IA32_SUPPORT
if (IS_IA32_PROCESS(ia64_task_regs(current))) {
ia32_drop_partial_page_list(current);
current->thread.task_size = IA32_PAGE_OFFSET;
set_fs(USER_DS);
}
+#endif
}
/*
*/
void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
default:
panic
("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
*/
uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
default:
panic
("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
return ret;
*/
void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
uint64_t addr)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
*/
uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
uint64_t ret = 0;
if (pcibus_info) {
__sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
break;
default:
- panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr);
+ panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
}
}
void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
uint64_t val)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
}
-uint64_t *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
+uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
{
- union br_ptr *ptr = (union br_ptr *)pcibus_info->pbi_buscommon.bs_base;
- uint64_t *ret = (uint64_t *) 0;
+ union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
+ uint64_t __iomem *ret = NULL;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
default:
panic
("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
- (void *)ptr);
+ ptr);
}
}
return ret;
uint64_t offset;
struct page *tmp;
struct tioca_common *tioca_common;
- struct tioca *ca_base;
+ struct tioca __iomem *ca_base;
tioca_common = tioca_kern->ca_common;
- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
if (list_empty(tioca_kern->ca_devices))
return 0;
{
int cap_ptr;
uint32_t reg;
- struct tioca *tioca_base;
+ struct tioca __iomem *tioca_base;
struct pci_dev *pdev;
struct tioca_common *common;
* Set ca's fw to match
*/
- tioca_base = (struct tioca *)common->ca_common.bs_base;
+ tioca_base = (struct tioca __iomem*)common->ca_common.bs_base;
__sn_setq_relaxed(&tioca_base->ca_control1, CA_AGP_FW_ENABLE);
}
tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
{
struct tioca_common *tioca_common;
- struct tioca *ca_base;
+ struct tioca __iomem *ca_base;
uint64_t ct_addr;
dma_addr_t bus_addr;
uint32_t node_upper;
struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(pdev);
tioca_common = (struct tioca_common *)pcidev_info->pdi_pcibus_info;
- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
ct_addr = PHYS_TO_TIODMA(paddr);
if (!ct_addr)
#define OVERRIDE_MACHINE 0
#endif
-static inline int override_machine(char *mach)
+static inline int override_machine(char __user *mach)
{
if (OVERRIDE_MACHINE) {
/* change ppc64 to ppc */
#include <asm/oplib.h>
#include <asm/bpp.h>
-struct linux_ebus *ebus_chain = 0;
+struct linux_ebus *ebus_chain = NULL;
/* We are together with pcic.c under CONFIG_PCI. */
extern unsigned int pcic_pin_to_irq(unsigned int, char *name);
{ "SUNW,CS4231", 0 },
{ "parallel", 0 },
{ "se", 2 },
- { 0, 0 }
+ { NULL, 0 }
};
/*
*/
static struct ebus_system_entry ebus_blacklist[] = {
{ "SUNW,JavaEngine1", je1_1 },
- { 0, 0 }
+ { NULL, NULL }
};
static struct ebus_device_irq *ebus_blackp = NULL;
ebus_alloc(sizeof(struct linux_ebus_child));
child = dev->children;
- child->next = 0;
+ child->next = NULL;
child->parent = dev;
child->bus = dev->bus;
fill_ebus_child(node, ®s[0], child);
ebus_alloc(sizeof(struct linux_ebus_child));
child = child->next;
- child->next = 0;
+ child->next = NULL;
child->parent = dev;
child->bus = dev->bus;
fill_ebus_child(node, ®s[0], child);
}
}
- pdev = pci_get_device(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_EBUS, 0);
+ pdev = pci_get_device(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_EBUS, NULL);
if (!pdev) {
return;
}
ebus_chain = ebus = (struct linux_ebus *)
ebus_alloc(sizeof(struct linux_ebus));
- ebus->next = 0;
+ ebus->next = NULL;
while (ebusnd) {
ebus_alloc(sizeof(struct linux_ebus_device));
dev = ebus->devices;
- dev->next = 0;
- dev->children = 0;
+ dev->next = NULL;
+ dev->children = NULL;
dev->bus = ebus;
fill_ebus_device(nd, dev);
ebus_alloc(sizeof(struct linux_ebus_device));
dev = dev->next;
- dev->next = 0;
- dev->children = 0;
+ dev->next = NULL;
+ dev->children = NULL;
dev->bus = ebus;
fill_ebus_device(nd, dev);
}
ebus->next = (struct linux_ebus *)
ebus_alloc(sizeof(struct linux_ebus));
ebus = ebus->next;
- ebus->next = 0;
+ ebus->next = NULL;
++num_ebus;
}
if (pdev)
return len;
}
-static int led_write_proc(struct file *file, const char *buffer,
+static int led_write_proc(struct file *file, const char __user *buffer,
unsigned long count, void *data)
{
char *buf = NULL;
static int pcic0_up;
static struct linux_pcic pcic0;
-void * __iomem pcic_regs;
+void __iomem *pcic_regs;
volatile int pcic_speculative;
volatile int pcic_trapped;
enum sparc_clock_type sp_clock_typ;
DEFINE_SPINLOCK(mostek_lock);
void __iomem *mstk48t02_regs = NULL;
-static struct mostek48t08 *mstk48t08_regs = NULL;
+static struct mostek48t08 __iomem *mstk48t08_regs = NULL;
static int set_rtc_mmss(unsigned long);
static int sbus_do_settimeofday(struct timespec *tv);
/* XXX r/o attribute is somewhere in r.flags */
r.flags = clk_reg[0].which_io;
r.start = clk_reg[0].phys_addr;
- mstk48t08_regs = (struct mostek48t08 *) sbus_ioremap(&r, 0,
+ mstk48t08_regs = sbus_ioremap(&r, 0,
sizeof(struct mostek48t08), "mk48t08");
mstk48t02_regs = &mstk48t08_regs->regs;
patch_kernel_fault_handler();
}
-volatile unsigned long *sun4c_memerr_reg = NULL;
+volatile unsigned long __iomem *sun4c_memerr_reg = NULL;
void __init sun4c_probe_memerr_reg(void)
{
if (!tsk_used_math(tsk))
return 0;
if (!regs)
- regs = (struct pt_regs *)tsk->thread.rsp0;
- --regs;
+ regs = ((struct pt_regs *)tsk->thread.rsp0) - 1;
if (tsk == current)
unlazy_fpu(tsk);
set_fs(KERNEL_DS);
if (cpu == 0)
return -EBUSY;
- disable_APIC_timer();
+ clear_local_APIC();
/*
* HACK:
unsigned int cpu_khz; /* TSC clocks / usec, not used here */
static unsigned long hpet_period; /* fsecs / HPET clock */
unsigned long hpet_tick; /* HPET clocks / interrupt */
-static int hpet_use_timer;
+static int hpet_use_timer; /* Use counter of hpet for time keeping, otherwise PIT */
unsigned long vxtime_hz = PIT_TICK_RATE;
int report_lost_ticks; /* command line option */
unsigned long long monotonic_base;
if (!hpet_init())
vxtime_hz = (1000000000000000L + hpet_period / 2) /
hpet_period;
+ else
+ vxtime.hpet_address = 0;
if (hpet_use_timer) {
cpu_khz = hpet_calibrate_tsc();
timename = "HPET";
#ifdef CONFIG_X86_PM_TIMER
- } else if (pmtmr_ioport) {
+ } else if (pmtmr_ioport && !vxtime.hpet_address) {
vxtime_hz = PM_TIMER_FREQUENCY;
timename = "PM";
pit_init();
return __ioremap(phys_addr, size, _PAGE_PCD);
}
+/**
+ * iounmap - Free a IO remapping
+ * @addr: virtual address from ioremap_*
+ *
+ * Caller must ensure there is only one unmapping for the same pointer.
+ */
void iounmap(volatile void __iomem *addr)
{
- struct vm_struct *p;
+ struct vm_struct *p, *o;
if (addr <= high_memory)
return;
addr < phys_to_virt(ISA_END_ADDRESS))
return;
- write_lock(&vmlist_lock);
- p = __remove_vm_area((void *)((unsigned long)addr & PAGE_MASK));
- if (!p)
+ addr = (volatile void __iomem *)(PAGE_MASK & (unsigned long __force)addr);
+ /* Use the vm area unlocked, assuming the caller
+ ensures there isn't another iounmap for the same address
+ in parallel. Reuse of the virtual address is prevented by
+ leaving it in the global lists until we're done with it.
+ cpa takes care of the direct mappings. */
+ read_lock(&vmlist_lock);
+ for (p = vmlist; p; p = p->next) {
+ if (p->addr == addr)
+ break;
+ }
+ read_unlock(&vmlist_lock);
+
+ if (!p) {
printk("iounmap: bad address %p\n", addr);
- else if (p->flags >> 20)
+ dump_stack();
+ return;
+ }
+
+ /* Reset the direct mapping. Can block */
+ if (p->flags >> 20)
ioremap_change_attr(p->phys_addr, p->size, 0);
- write_unlock(&vmlist_lock);
+
+ /* Finally remove it */
+ o = remove_vm_area((void *)addr);
+ BUG_ON(p != o || o == NULL);
kfree(p);
}
int res = -1;
unsigned long addr, end;
+ if (shift >= 64)
+ return -1;
memset(memnodemap, 0xff, sizeof(memnodemap));
for (i = 0; i < numnodes; i++) {
addr = nodes[i].start;
if (memnodemap[addr >> shift] != 0xff)
return -1;
memnodemap[addr >> shift] = i;
- addr += (1 << shift);
+ addr += (1UL << shift);
} while (addr < end);
res = 1;
}
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
+#include <linux/bitmap.h>
#include "pci.h"
#define MMCONFIG_APER_SIZE (256*1024*1024)
+static DECLARE_BITMAP(fallback_slots, 32);
+
/* Static virtual mapping of the MMCONFIG aperture */
struct mmcfg_virt {
struct acpi_table_mcfg_config *cfg;
- char *virt;
+ char __iomem *virt;
};
static struct mmcfg_virt *pci_mmcfg_virt;
-static char *get_virt(unsigned int seg, int bus)
+static char __iomem *get_virt(unsigned int seg, unsigned bus)
{
int cfg_num = -1;
struct acpi_table_mcfg_config *cfg;
while (1) {
++cfg_num;
if (cfg_num >= pci_mmcfg_config_num) {
- /* something bad is going on, no cfg table is found. */
- /* so we fall back to the old way we used to do this */
- /* and just rely on the first entry to be correct. */
- return pci_mmcfg_virt[0].virt;
+ /* Not found - fall back to type 1. This happens
+ e.g. on the internal devices of a K8 northbridge. */
+ return NULL;
}
cfg = pci_mmcfg_virt[cfg_num].cfg;
if (cfg->pci_segment_group_number != seg)
}
}
-static inline char *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
+static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
-
- return get_virt(seg, bus) + ((bus << 20) | (devfn << 12));
+ char __iomem *addr;
+ if (seg == 0 && bus == 0 && test_bit(PCI_SLOT(devfn), &fallback_slots))
+ return NULL;
+ addr = get_virt(seg, bus);
+ if (!addr)
+ return NULL;
+ return addr + ((bus << 20) | (devfn << 12));
}
static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
- char *addr = pci_dev_base(seg, bus, devfn);
+ char __iomem *addr;
+ /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
if (unlikely(!value || (bus > 255) || (devfn > 255) || (reg > 4095)))
return -EINVAL;
+ addr = pci_dev_base(seg, bus, devfn);
+ if (!addr)
+ return pci_conf1_read(seg,bus,devfn,reg,len,value);
+
switch (len) {
case 1:
*value = readb(addr + reg);
static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 value)
{
- char *addr = pci_dev_base(seg, bus, devfn);
+ char __iomem *addr;
+ /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
return -EINVAL;
+ addr = pci_dev_base(seg, bus, devfn);
+ if (!addr)
+ return pci_conf1_write(seg,bus,devfn,reg,len,value);
+
switch (len) {
case 1:
writeb(value, addr + reg);
.write = pci_mmcfg_write,
};
+/* K8 systems have some devices (typically in the builtin northbridge)
+ that are only accessible using type1
+ Normally this can be expressed in the MCFG by not listing them
+ and assigning suitable _SEGs, but this isn't implemented in some BIOS.
+ Instead try to discover all devices on bus 0 that are unreachable using MM
+ and fallback for them.
+ We only do this for bus 0/seg 0 */
+static __init void unreachable_devices(void)
+{
+ int i;
+ for (i = 0; i < 32; i++) {
+ u32 val1;
+ char __iomem *addr;
+
+ pci_conf1_read(0, 0, PCI_DEVFN(i,0), 0, 4, &val1);
+ if (val1 == 0xffffffff)
+ continue;
+ addr = pci_dev_base(0, 0, PCI_DEVFN(i, 0));
+ if (addr == NULL|| readl(addr) != val1) {
+ set_bit(i, &fallback_slots);
+ }
+ }
+}
+
static int __init pci_mmcfg_init(void)
{
int i;
printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
}
+ unreachable_devices();
+
raw_pci_ops = &pci_mmcfg;
pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
}
memset(adummy_dev, 0, sizeof(struct adummy_dev));
- atm_dev = atm_dev_register(DEV_LABEL, &adummy_ops, -1, 0);
+ atm_dev = atm_dev_register(DEV_LABEL, &adummy_ops, -1, NULL);
if (!atm_dev) {
printk(KERN_ERR DEV_LABEL ": atm_dev_register() failed\n");
err = -ENODEV;
static struct sysdev_class memory_sysdev_class = {
set_kset_name(MEMORY_CLASS_NAME),
};
-EXPORT_SYMBOL(memory_sysdev_class);
static char *memory_hotplug_name(struct kset *kset, struct kobject *kobj)
{
request_queue_t *q = disk->queue;
if (disk->flags & GENHD_FL_UP)
del_gendisk(disk);
- if (q)
+ if (q) {
blk_cleanup_queue(q);
+ drv->queue = NULL;
+ }
}
}
static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
{
drm_radeon_private_t *dev_priv = dev->dev_private;;
+ unsigned int mem_size;
+
DRM_DEBUG("\n");
dev_priv->is_pci = init->is_pci;
+ dev_priv->fb_location) >> 10));
dev_priv->gart_size = init->gart_size;
- dev_priv->gart_vm_start = dev_priv->fb_location
- + RADEON_READ(RADEON_CONFIG_APER_SIZE);
+
+ mem_size = RADEON_READ(RADEON_CONFIG_MEMSIZE);
+ if (mem_size == 0)
+ mem_size = 0x800000;
+ dev_priv->gart_vm_start = dev_priv->fb_location + mem_size;
#if __OS_HAS_AGP
if (!dev_priv->is_pci)
# define RADEON_PLL_WR_EN (1 << 7)
#define RADEON_CLOCK_CNTL_INDEX 0x0008
#define RADEON_CONFIG_APER_SIZE 0x0108
+#define RADEON_CONFIG_MEMSIZE 0x00f8
#define RADEON_CRTC_OFFSET 0x0224
#define RADEON_CRTC_OFFSET_CNTL 0x0228
# define RADEON_CRTC_TILE_EN (1 << 15)
new_smi->handlers->cleanup(new_smi->si_sm);
kfree(new_smi->si_sm);
}
- new_smi->io_cleanup(new_smi);
+ if (new_smi->io_cleanup)
+ new_smi->io_cleanup(new_smi);
return rv;
}
kfree(to_clean->si_sm);
- to_clean->io_cleanup(to_clean);
+ if (to_clean->io_cleanup)
+ to_clean->io_cleanup(to_clean);
}
static __exit void cleanup_ipmi_si(void)
typedef struct _MW_READWRITE {
unsigned short usDspAddress; /* The dsp address */
unsigned long ulDataLength; /* The size in bytes of the data or user buffer */
- void *pBuf; /* Input:variable sized buffer */
+ void __user *pBuf; /* Input:variable sized buffer */
} MW_READWRITE, *pMW_READWRITE;
#define IOCTL_MW_RESET _IO(MWAVE_MINOR,1)
dev_link_t *link;
int size;
int rc;
+ void __user *argp = (void __user *)arg;
#ifdef PCMCIA_DEBUG
char *ioctl_names[CM_IOC_MAXNR + 1] = {
[_IOC_NR(CM_IOCGSTATUS)] "CM_IOCGSTATUS",
_IOC_DIR(cmd), _IOC_READ, _IOC_WRITE, size, cmd);
if (_IOC_DIR(cmd) & _IOC_READ) {
- if (!access_ok(VERIFY_WRITE, (void *)arg, size))
+ if (!access_ok(VERIFY_WRITE, argp, size))
return -EFAULT;
}
if (_IOC_DIR(cmd) & _IOC_WRITE) {
- if (!access_ok(VERIFY_READ, (void *)arg, size))
+ if (!access_ok(VERIFY_READ, argp, size))
return -EFAULT;
}
status |= CM_NO_READER;
if (test_bit(IS_BAD_CARD, &dev->flags))
status |= CM_BAD_CARD;
- if (copy_to_user((int *)arg, &status, sizeof(int)))
+ if (copy_to_user(argp, &status, sizeof(int)))
return -EFAULT;
}
return 0;
case CM_IOCGATR:
DEBUGP(4, dev, "... in CM_IOCGATR\n");
{
- struct atreq *atreq = (struct atreq *) arg;
+ struct atreq __user *atreq = argp;
int tmp;
/* allow nonblocking io and being interrupted */
if (wait_event_interruptible
{
struct ptsreq krnptsreq;
- if (copy_from_user(&krnptsreq, (struct ptsreq *) arg,
+ if (copy_from_user(&krnptsreq, argp,
sizeof(struct ptsreq)))
return -EFAULT;
int old_pc_debug = 0;
old_pc_debug = pc_debug;
- if (copy_from_user(&pc_debug, (int *)arg, sizeof(int)))
+ if (copy_from_user(&pc_debug, argp, sizeof(int)))
return -EFAULT;
if (old_pc_debug != pc_debug)
/*
* booke_wdt_write:
*/
-static ssize_t booke_wdt_write (struct file *file, const char *buf,
+static ssize_t booke_wdt_write (struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
booke_wdt_ping();
unsigned int cmd, unsigned long arg)
{
u32 tmp = 0;
+ u32 __user *p = (u32 __user *)arg;
switch (cmd) {
case WDIOC_GETSUPPORT:
- if (copy_to_user ((struct watchdog_info *) arg, &ident,
+ if (copy_to_user ((struct watchdog_info __user *) arg, &ident,
sizeof(struct watchdog_info)))
return -EFAULT;
case WDIOC_GETSTATUS:
- return put_user(ident.options, (u32 *) arg);
+ return put_user(ident.options, p);
case WDIOC_GETBOOTSTATUS:
/* XXX: something is clearing TSR */
tmp = mfspr(SPRN_TSR) & TSR_WRS(3);
booke_wdt_ping();
return 0;
case WDIOC_SETTIMEOUT:
- if (get_user(booke_wdt_period, (u32 *) arg))
+ if (get_user(booke_wdt_period, p))
return -EFAULT;
mtspr(SPRN_TCR, (mfspr(SPRN_TCR)&~WDTP(0))|WDTP(booke_wdt_period));
return 0;
case WDIOC_GETTIMEOUT:
- return put_user(booke_wdt_period, (u32 *) arg);
+ return put_user(booke_wdt_period, p);
case WDIOC_SETOPTIONS:
- if (get_user(tmp, (u32 *) arg))
+ if (get_user(tmp, p))
return -EINVAL;
if (tmp == WDIOS_ENABLECARD) {
booke_wdt_ping();
wdrtas_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
- int __user *argp = (void *)arg;
+ int __user *argp = (void __user *)arg;
int i;
static struct watchdog_info wdinfo = {
.options = WDRTAS_SUPPORTED_MASK,
int ordernum = 0;
int retval = 0;
unsigned int packet_array_size = 0;
- void **invalid_addr_packet_array = 0;
- void *packet_data_temp_buf = 0;
+ void **invalid_addr_packet_array = NULL;
+ void *packet_data_temp_buf = NULL;
unsigned int idx = 0;
pr_debug("create_packet: entry \n");
packet_data_temp_buf),
allocation_floor);
invalid_addr_packet_array[idx++] = packet_data_temp_buf;
- packet_data_temp_buf = 0;
+ packet_data_temp_buf = NULL;
}
}
spin_lock(&rbu_data.lock);
i2c_set_adapdata(&drv_data->adapter, drv_data);
if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
- MV64XXX_I2C_CTLR_NAME, drv_data)) {
-
- dev_err(dev, "mv64xxx: Can't register intr handler "
- "irq: %d\n", drv_data->irq);
+ MV64XXX_I2C_CTLR_NAME, drv_data)) {
+ dev_err(&drv_data->adapter.dev,
+ "mv64xxx: Can't register intr handler irq: %d\n",
+ drv_data->irq);
rc = -EINVAL;
goto exit_unmap_regs;
} else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) {
- dev_err(dev, "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
+ dev_err(&drv_data->adapter.dev,
+ "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
goto exit_free_irq;
}
depends on SOC_AU1200 && BLK_DEV_IDE_AU1XXX
endchoice
-config BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
- bool "Enable burstable Mode on DbDMA"
- default false
- depends BLK_DEV_IDE_AU1XXX
- help
- This option enable the burstable Flag on DbDMA controller
- (cf. "AMD Alchemy 'Au1200' Processor Data Book - PRELIMINARY").
-
config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
int "Maximum transfer size (KB) per request (up to 128)"
default "128"
config BLK_DEV_MPC8xx_IDE
bool "MPC8xx IDE support"
- depends on 8xx
+ depends on 8xx && IDE=y && BLK_DEV_IDE=y
help
This option provides support for IDE on Motorola MPC8xx Systems.
Please see 'Type of MPC8xx IDE interface' for details.
struct cdrom_info *info = drive->driver_data;
info->dma = 0;
- info->cmd = 0;
info->start_seek = jiffies;
return cdrom_start_packet_command(drive, 0, cdrom_start_seek_continuation);
}
(rq->nr_sectors & (sectors_per_frame - 1)))
info->dma = 0;
- info->cmd = READ;
-
/* Start sending the read request to the drive. */
return cdrom_start_packet_command(drive, 32768, cdrom_start_read_continuation);
}
struct cdrom_info *info = drive->driver_data;
info->dma = 0;
- info->cmd = 0;
rq->flags &= ~REQ_FAILED;
len = rq->data_len;
/* use dma, if possible. we don't need to check more, since we
* know that the transfer is always (at least!) frame aligned */
info->dma = drive->using_dma ? 1 : 0;
- info->cmd = WRITE;
info->devinfo.media_written = 1;
rq->flags |= REQ_QUIET;
info->dma = 0;
- info->cmd = 0;
/*
* sg request
int mask = drive->queue->dma_alignment;
unsigned long addr = (unsigned long) page_address(bio_page(rq->bio));
- info->cmd = rq_data_dir(rq);
info->dma = drive->using_dma;
/*
struct request request_sense_request;
int dma;
- int cmd;
unsigned long last_block;
unsigned long start_seek;
/* Buffer to hold mechanism status and changer slot table. */
struct ide_disk_obj *idkp = drive->driver_data;
struct gendisk *g = idkp->disk;
- ide_cacheflush_p(drive);
-
ide_unregister_subdriver(drive, idkp->driver);
del_gendisk(g);
+ ide_cacheflush_p(drive);
+
ide_disk_put(idkp);
return 0;
#include <asm/io.h>
#include <asm/irq.h>
-struct drive_list_entry {
- const char *id_model;
- const char *id_firmware;
-};
-
static const struct drive_list_entry drive_whitelist [] = {
{ "Micropolis 2112A" , "ALL" },
};
/**
- * in_drive_list - look for drive in black/white list
+ * ide_in_drive_list - look for drive in black/white list
* @id: drive identifier
* @drive_table: list to inspect
*
* Returns 1 if the drive is found in the table.
*/
-static int in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
+int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
{
for ( ; drive_table->id_model ; drive_table++)
if ((!strcmp(drive_table->id_model, id->model)) &&
return 0;
}
+EXPORT_SYMBOL_GPL(ide_in_drive_list);
+
/**
* ide_dma_intr - IDE DMA interrupt handler
* @drive: the drive the interrupt is for
{
struct hd_driveid *id = drive->id;
- int blacklist = in_drive_list(id, drive_blacklist);
+ int blacklist = ide_in_drive_list(id, drive_blacklist);
if (blacklist) {
printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
drive->name, id->model);
int __ide_dma_good_drive (ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
- return in_drive_list(id, drive_whitelist);
+ return ide_in_drive_list(id, drive_whitelist);
}
EXPORT_SYMBOL(__ide_dma_good_drive);
obj-$(CONFIG_BLK_DEV_IDE_SWARM) += swarm.o
+obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o
+
+EXTRA_CFLAGS := -Idrivers/ide
*/
#undef REALLY_SLOW_IO /* most systems can safely undef this */
-#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */
#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/ioport.h>
-#include <linux/hdreg.h>
+#include <linux/platform_device.h>
+
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/sysdev.h>
#include <linux/dma-mapping.h>
+#include "ide-timing.h"
+
#include <asm/io.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
-#if CONFIG_PM
-#include <asm/mach-au1x00/au1xxx_pm.h>
-#endif
-
#include <asm/mach-au1x00/au1xxx_ide.h>
#define DRV_NAME "au1200-ide"
#define DRV_VERSION "1.0"
-#define DRV_AUTHOR "AMD PCS / Pete Popov <ppopov@embeddedalley.com>"
-#define DRV_DESC "Au1200 IDE"
-
-static _auide_hwif auide_hwif;
-static spinlock_t ide_tune_drive_spin_lock = SPIN_LOCK_UNLOCKED;
-static spinlock_t ide_tune_chipset_spin_lock = SPIN_LOCK_UNLOCKED;
-static int dbdma_init_done = 0;
-
-/*
- * local I/O functions
- */
-u8 auide_inb(unsigned long port)
-{
- return (au_readb(port));
-}
+#define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
-u16 auide_inw(unsigned long port)
-{
- return (au_readw(port));
-}
+/* enable the burstmode in the dbdma */
+#define IDE_AU1XXX_BURSTMODE 1
-u32 auide_inl(unsigned long port)
-{
- return (au_readl(port));
-}
+static _auide_hwif auide_hwif;
+static int dbdma_init_done;
-void auide_insw(unsigned long port, void *addr, u32 count)
-{
#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
- _auide_hwif *ahwif = &auide_hwif;
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
-
- if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
- DDMA_FLAGS_NOIE)) {
- printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
- return;
- }
- ctp = *((chan_tab_t **)ahwif->rx_chan);
- dp = ctp->cur_ptr;
- while (dp->dscr_cmd0 & DSCR_CMD0_V)
- ;
- ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
-#else
- while (count--)
- {
- *(u16 *)addr = au_readw(port);
- addr +=2 ;
- }
-#endif
-}
-
-void auide_insl(unsigned long port, void *addr, u32 count)
-{
- while (count--)
- {
- *(u32 *)addr = au_readl(port);
- /* NOTE: For IDE interfaces over PCMCIA,
- * 32-bit access does not work
- */
- addr += 4;
- }
-}
-
-void auide_outb(u8 addr, unsigned long port)
+void auide_insw(unsigned long port, void *addr, u32 count)
{
- return (au_writeb(addr, port));
-}
+ _auide_hwif *ahwif = &auide_hwif;
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
-void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
-{
- return (au_writeb(addr, port));
+ if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
+ DDMA_FLAGS_NOIE)) {
+ printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
+ return;
+ }
+ ctp = *((chan_tab_t **)ahwif->rx_chan);
+ dp = ctp->cur_ptr;
+ while (dp->dscr_cmd0 & DSCR_CMD0_V)
+ ;
+ ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}
-void auide_outw(u16 addr, unsigned long port)
+void auide_outsw(unsigned long port, void *addr, u32 count)
{
- return (au_writew(addr, port));
-}
+ _auide_hwif *ahwif = &auide_hwif;
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
-void auide_outl(u32 addr, unsigned long port)
-{
- return (au_writel(addr, port));
+ if(!put_source_flags(ahwif->tx_chan, (void*)addr,
+ count << 1, DDMA_FLAGS_NOIE)) {
+ printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
+ return;
+ }
+ ctp = *((chan_tab_t **)ahwif->tx_chan);
+ dp = ctp->cur_ptr;
+ while (dp->dscr_cmd0 & DSCR_CMD0_V)
+ ;
+ ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
}
-void auide_outsw(unsigned long port, void *addr, u32 count)
-{
-#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
- _auide_hwif *ahwif = &auide_hwif;
- chan_tab_t *ctp;
- au1x_ddma_desc_t *dp;
-
- if(!put_source_flags(ahwif->tx_chan, (void*)addr,
- count << 1, DDMA_FLAGS_NOIE)) {
- printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
- return;
- }
- ctp = *((chan_tab_t **)ahwif->tx_chan);
- dp = ctp->cur_ptr;
- while (dp->dscr_cmd0 & DSCR_CMD0_V)
- ;
- ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
-#else
- while (count--)
- {
- au_writew(*(u16 *)addr, port);
- addr += 2;
- }
#endif
-}
-
-void auide_outsl(unsigned long port, void *addr, u32 count)
-{
- while (count--)
- {
- au_writel(*(u32 *)addr, port);
- /* NOTE: For IDE interfaces over PCMCIA,
- * 32-bit access does not work
- */
- addr += 4;
- }
-}
static void auide_tune_drive(ide_drive_t *drive, byte pio)
{
- int mem_sttime;
- int mem_stcfg;
- unsigned long flags;
- u8 speed;
-
- /* get the best pio mode for the drive */
- pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
-
- printk("%s: setting Au1XXX IDE to PIO mode%d\n",
- drive->name, pio);
-
- spin_lock_irqsave(&ide_tune_drive_spin_lock, flags);
-
- mem_sttime = 0;
- mem_stcfg = au_readl(MEM_STCFG2);
-
- /* set pio mode! */
- switch(pio) {
- case 0:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_PIO0_TWCS
- | SBC_IDE_PIO0_TCSH
- | SBC_IDE_PIO0_TCSOFF
- | SBC_IDE_PIO0_TWP
- | SBC_IDE_PIO0_TCSW
- | SBC_IDE_PIO0_TPM
- | SBC_IDE_PIO0_TA;
- /* set configuration for RCS2# */
- mem_stcfg |= TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
-
- au_writel(mem_sttime,MEM_STTIME2);
- au_writel(mem_stcfg,MEM_STCFG2);
- break;
-
- case 1:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_PIO1_TWCS
- | SBC_IDE_PIO1_TCSH
- | SBC_IDE_PIO1_TCSOFF
- | SBC_IDE_PIO1_TWP
- | SBC_IDE_PIO1_TCSW
- | SBC_IDE_PIO1_TPM
- | SBC_IDE_PIO1_TA;
- /* set configuration for RCS2# */
- mem_stcfg |= TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
- break;
-
- case 2:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_PIO2_TWCS
- | SBC_IDE_PIO2_TCSH
- | SBC_IDE_PIO2_TCSOFF
- | SBC_IDE_PIO2_TWP
- | SBC_IDE_PIO2_TCSW
- | SBC_IDE_PIO2_TPM
- | SBC_IDE_PIO2_TA;
- /* set configuration for RCS2# */
- mem_stcfg &= ~TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
- break;
-
- case 3:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_PIO3_TWCS
- | SBC_IDE_PIO3_TCSH
- | SBC_IDE_PIO3_TCSOFF
- | SBC_IDE_PIO3_TWP
- | SBC_IDE_PIO3_TCSW
- | SBC_IDE_PIO3_TPM
- | SBC_IDE_PIO3_TA;
- /* set configuration for RCS2# */
- mem_stcfg |= TS_MASK;
- mem_stcfg &= ~TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
-
- break;
-
- case 4:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_PIO4_TWCS
- | SBC_IDE_PIO4_TCSH
- | SBC_IDE_PIO4_TCSOFF
- | SBC_IDE_PIO4_TWP
- | SBC_IDE_PIO4_TCSW
- | SBC_IDE_PIO4_TPM
- | SBC_IDE_PIO4_TA;
- /* set configuration for RCS2# */
- mem_stcfg &= ~TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
- break;
- }
-
- au_writel(mem_sttime,MEM_STTIME2);
- au_writel(mem_stcfg,MEM_STCFG2);
-
- spin_unlock_irqrestore(&ide_tune_drive_spin_lock, flags);
-
- speed = pio + XFER_PIO_0;
- ide_config_drive_speed(drive, speed);
+ int mem_sttime;
+ int mem_stcfg;
+ u8 speed;
+
+ /* get the best pio mode for the drive */
+ pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
+
+ printk(KERN_INFO "%s: setting Au1XXX IDE to PIO mode%d\n",
+ drive->name, pio);
+
+ mem_sttime = 0;
+ mem_stcfg = au_readl(MEM_STCFG2);
+
+ /* set pio mode! */
+ switch(pio) {
+ case 0:
+ mem_sttime = SBC_IDE_TIMING(PIO0);
+
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
+ break;
+
+ case 1:
+ mem_sttime = SBC_IDE_TIMING(PIO1);
+
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
+ break;
+
+ case 2:
+ mem_sttime = SBC_IDE_TIMING(PIO2);
+
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
+ break;
+
+ case 3:
+ mem_sttime = SBC_IDE_TIMING(PIO3);
+
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
+
+ break;
+
+ case 4:
+ mem_sttime = SBC_IDE_TIMING(PIO4);
+
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
+ break;
+ }
+
+ au_writel(mem_sttime,MEM_STTIME2);
+ au_writel(mem_stcfg,MEM_STCFG2);
+
+ speed = pio + XFER_PIO_0;
+ ide_config_drive_speed(drive, speed);
}
static int auide_tune_chipset (ide_drive_t *drive, u8 speed)
{
- u8 mode = 0;
- int mem_sttime;
- int mem_stcfg;
- unsigned long flags;
+ int mem_sttime;
+ int mem_stcfg;
+ unsigned long mode;
+
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- struct hd_driveid *id = drive->id;
-
- /*
- * Now see what the current drive is capable of,
- * selecting UDMA only if the mate said it was ok.
- */
- if (id && (id->capability & 1) && drive->autodma &&
- !__ide_dma_bad_drive(drive)) {
- if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
- if (id->dma_mword & 4)
- mode = XFER_MW_DMA_2;
- else if (id->dma_mword & 2)
- mode = XFER_MW_DMA_1;
- else if (id->dma_mword & 1)
- mode = XFER_MW_DMA_0;
- }
- }
+ if (ide_use_dma(drive))
+ mode = ide_dma_speed(drive, 0);
#endif
- spin_lock_irqsave(&ide_tune_chipset_spin_lock, flags);
+ mem_sttime = 0;
+ mem_stcfg = au_readl(MEM_STCFG2);
- mem_sttime = 0;
- mem_stcfg = au_readl(MEM_STCFG2);
-
- switch(speed) {
- case XFER_PIO_4:
- case XFER_PIO_3:
- case XFER_PIO_2:
- case XFER_PIO_1:
- case XFER_PIO_0:
- auide_tune_drive(drive, (speed - XFER_PIO_0));
- break;
+ if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
+ auide_tune_drive(drive, speed - XFER_PIO_0);
+ return 0;
+ }
+
+ switch(speed) {
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- case XFER_MW_DMA_2:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_MDMA2_TWCS
- | SBC_IDE_MDMA2_TCSH
- | SBC_IDE_MDMA2_TCSOFF
- | SBC_IDE_MDMA2_TWP
- | SBC_IDE_MDMA2_TCSW
- | SBC_IDE_MDMA2_TPM
- | SBC_IDE_MDMA2_TA;
- /* set configuration for RCS2# */
- mem_stcfg &= ~TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
-
- mode = XFER_MW_DMA_2;
- break;
- case XFER_MW_DMA_1:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_MDMA1_TWCS
- | SBC_IDE_MDMA1_TCSH
- | SBC_IDE_MDMA1_TCSOFF
- | SBC_IDE_MDMA1_TWP
- | SBC_IDE_MDMA1_TCSW
- | SBC_IDE_MDMA1_TPM
- | SBC_IDE_MDMA1_TA;
- /* set configuration for RCS2# */
- mem_stcfg &= ~TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
-
- mode = XFER_MW_DMA_1;
- break;
- case XFER_MW_DMA_0:
- /* set timing parameters for RCS2# */
- mem_sttime = SBC_IDE_MDMA0_TWCS
- | SBC_IDE_MDMA0_TCSH
- | SBC_IDE_MDMA0_TCSOFF
- | SBC_IDE_MDMA0_TWP
- | SBC_IDE_MDMA0_TCSW
- | SBC_IDE_MDMA0_TPM
- | SBC_IDE_MDMA0_TA;
- /* set configuration for RCS2# */
- mem_stcfg |= TS_MASK;
- mem_stcfg &= ~TCSOE_MASK;
- mem_stcfg &= ~TOECS_MASK;
- mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
-
- mode = XFER_MW_DMA_0;
- break;
+ case XFER_MW_DMA_2:
+ mem_sttime = SBC_IDE_TIMING(MDMA2);
+
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
+
+ mode = XFER_MW_DMA_2;
+ break;
+ case XFER_MW_DMA_1:
+ mem_sttime = SBC_IDE_TIMING(MDMA1);
+
+ /* set configuration for RCS2# */
+ mem_stcfg &= ~TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
+
+ mode = XFER_MW_DMA_1;
+ break;
+ case XFER_MW_DMA_0:
+ mem_sttime = SBC_IDE_TIMING(MDMA0);
+
+ /* set configuration for RCS2# */
+ mem_stcfg |= TS_MASK;
+ mem_stcfg &= ~TCSOE_MASK;
+ mem_stcfg &= ~TOECS_MASK;
+ mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
+
+ mode = XFER_MW_DMA_0;
+ break;
#endif
- default:
- return 1;
- }
-
- /*
- * Tell the drive to switch to the new mode; abort on failure.
- */
- if (!mode || ide_config_drive_speed(drive, mode))
- {
- return 1; /* failure */
- }
-
-
- au_writel(mem_sttime,MEM_STTIME2);
- au_writel(mem_stcfg,MEM_STCFG2);
+ default:
+ return 1;
+ }
+
+ if (ide_config_drive_speed(drive, mode))
+ return 1;
- spin_unlock_irqrestore(&ide_tune_chipset_spin_lock, flags);
+ au_writel(mem_sttime,MEM_STTIME2);
+ au_writel(mem_stcfg,MEM_STCFG2);
- return 0;
+ return 0;
}
/*
* Multi-Word DMA + DbDMA functions
*/
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-static int in_drive_list(struct hd_driveid *id,
- const struct drive_list_entry *drive_table)
-{
- for ( ; drive_table->id_model ; drive_table++){
- if ((!strcmp(drive_table->id_model, id->model)) &&
- ((strstr(drive_table->id_firmware, id->fw_rev)) ||
- (!strcmp(drive_table->id_firmware, "ALL")))
- )
- return 1;
- }
- return 0;
-}
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
{
- ide_hwif_t *hwif = drive->hwif;
- _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
- struct scatterlist *sg = hwif->sg_table;
+ ide_hwif_t *hwif = drive->hwif;
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+ struct scatterlist *sg = hwif->sg_table;
- ide_map_sg(drive, rq);
+ ide_map_sg(drive, rq);
- if (rq_data_dir(rq) == READ)
- hwif->sg_dma_direction = DMA_FROM_DEVICE;
- else
- hwif->sg_dma_direction = DMA_TO_DEVICE;
+ if (rq_data_dir(rq) == READ)
+ hwif->sg_dma_direction = DMA_FROM_DEVICE;
+ else
+ hwif->sg_dma_direction = DMA_TO_DEVICE;
- return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
- hwif->sg_dma_direction);
+ return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
+ hwif->sg_dma_direction);
}
static int auide_build_dmatable(ide_drive_t *drive)
{
- int i, iswrite, count = 0;
- ide_hwif_t *hwif = HWIF(drive);
-
- struct request *rq = HWGROUP(drive)->rq;
-
- _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
- struct scatterlist *sg;
-
- iswrite = (rq_data_dir(rq) == WRITE);
- /* Save for interrupt context */
- ahwif->drive = drive;
-
- /* Build sglist */
- hwif->sg_nents = i = auide_build_sglist(drive, rq);
-
- if (!i)
- return 0;
-
- /* fill the descriptors */
- sg = hwif->sg_table;
- while (i && sg_dma_len(sg)) {
- u32 cur_addr;
- u32 cur_len;
-
- cur_addr = sg_dma_address(sg);
- cur_len = sg_dma_len(sg);
-
- while (cur_len) {
- u32 flags = DDMA_FLAGS_NOIE;
- unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
-
- if (++count >= PRD_ENTRIES) {
- printk(KERN_WARNING "%s: DMA table too small\n",
- drive->name);
- goto use_pio_instead;
- }
-
- /* Lets enable intr for the last descriptor only */
- if (1==i)
- flags = DDMA_FLAGS_IE;
- else
- flags = DDMA_FLAGS_NOIE;
-
- if (iswrite) {
- if(!put_source_flags(ahwif->tx_chan,
- (void*)(page_address(sg->page)
- + sg->offset),
- tc, flags)) {
- printk(KERN_ERR "%s failed %d\n",
- __FUNCTION__, __LINE__);
+ int i, iswrite, count = 0;
+ ide_hwif_t *hwif = HWIF(drive);
+
+ struct request *rq = HWGROUP(drive)->rq;
+
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+ struct scatterlist *sg;
+
+ iswrite = (rq_data_dir(rq) == WRITE);
+ /* Save for interrupt context */
+ ahwif->drive = drive;
+
+ /* Build sglist */
+ hwif->sg_nents = i = auide_build_sglist(drive, rq);
+
+ if (!i)
+ return 0;
+
+ /* fill the descriptors */
+ sg = hwif->sg_table;
+ while (i && sg_dma_len(sg)) {
+ u32 cur_addr;
+ u32 cur_len;
+
+ cur_addr = sg_dma_address(sg);
+ cur_len = sg_dma_len(sg);
+
+ while (cur_len) {
+ u32 flags = DDMA_FLAGS_NOIE;
+ unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
+
+ if (++count >= PRD_ENTRIES) {
+ printk(KERN_WARNING "%s: DMA table too small\n",
+ drive->name);
+ goto use_pio_instead;
+ }
+
+ /* Lets enable intr for the last descriptor only */
+ if (1==i)
+ flags = DDMA_FLAGS_IE;
+ else
+ flags = DDMA_FLAGS_NOIE;
+
+ if (iswrite) {
+ if(!put_source_flags(ahwif->tx_chan,
+ (void*)(page_address(sg->page)
+ + sg->offset),
+ tc, flags)) {
+ printk(KERN_ERR "%s failed %d\n",
+ __FUNCTION__, __LINE__);
}
- } else
+ } else
{
- if(!put_dest_flags(ahwif->rx_chan,
- (void*)(page_address(sg->page)
- + sg->offset),
- tc, flags)) {
- printk(KERN_ERR "%s failed %d\n",
- __FUNCTION__, __LINE__);
+ if(!put_dest_flags(ahwif->rx_chan,
+ (void*)(page_address(sg->page)
+ + sg->offset),
+ tc, flags)) {
+ printk(KERN_ERR "%s failed %d\n",
+ __FUNCTION__, __LINE__);
}
- }
+ }
- cur_addr += tc;
- cur_len -= tc;
- }
- sg++;
- i--;
- }
+ cur_addr += tc;
+ cur_len -= tc;
+ }
+ sg++;
+ i--;
+ }
- if (count)
- return 1;
+ if (count)
+ return 1;
-use_pio_instead:
- dma_unmap_sg(ahwif->dev,
- hwif->sg_table,
- hwif->sg_nents,
- hwif->sg_dma_direction);
+ use_pio_instead:
+ dma_unmap_sg(ahwif->dev,
+ hwif->sg_table,
+ hwif->sg_nents,
+ hwif->sg_dma_direction);
- return 0; /* revert to PIO for this request */
+ return 0; /* revert to PIO for this request */
}
static int auide_dma_end(ide_drive_t *drive)
{
- ide_hwif_t *hwif = HWIF(drive);
- _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
+ ide_hwif_t *hwif = HWIF(drive);
+ _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
- if (hwif->sg_nents) {
- dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
- hwif->sg_dma_direction);
- hwif->sg_nents = 0;
- }
+ if (hwif->sg_nents) {
+ dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
+ hwif->sg_dma_direction);
+ hwif->sg_nents = 0;
+ }
- return 0;
+ return 0;
}
static void auide_dma_start(ide_drive_t *drive )
{
-// printk("%s\n", __FUNCTION__);
}
-ide_startstop_t auide_dma_intr(ide_drive_t *drive)
-{
- //printk("%s\n", __FUNCTION__);
-
- u8 stat = 0, dma_stat = 0;
-
- dma_stat = HWIF(drive)->ide_dma_end(drive);
- stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
- if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
- if (!dma_stat) {
- struct request *rq = HWGROUP(drive)->rq;
-
- ide_end_request(drive, 1, rq->nr_sectors);
- return ide_stopped;
- }
- printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
- drive->name, dma_stat);
- }
- return ide_error(drive, "dma_intr", stat);
-}
static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
{
- //printk("%s\n", __FUNCTION__);
-
- /* issue cmd to drive */
- ide_execute_command(drive, command, &auide_dma_intr,
- (2*WAIT_CMD), NULL);
+ /* issue cmd to drive */
+ ide_execute_command(drive, command, &ide_dma_intr,
+ (2*WAIT_CMD), NULL);
}
static int auide_dma_setup(ide_drive_t *drive)
-{
-// printk("%s\n", __FUNCTION__);
-
- if (drive->media != ide_disk)
- return 1;
-
- if (!auide_build_dmatable(drive))
- /* try PIO instead of DMA */
- return 1;
+{
+ struct request *rq = HWGROUP(drive)->rq;
- drive->waiting_for_dma = 1;
+ if (!auide_build_dmatable(drive)) {
+ ide_map_sg(drive, rq);
+ return 1;
+ }
- return 0;
+ drive->waiting_for_dma = 1;
+ return 0;
}
static int auide_dma_check(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
+ u8 speed;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- if( !dbdma_init_done ){
- auide_hwif.white_list = in_drive_list(drive->id,
- dma_white_list);
- auide_hwif.black_list = in_drive_list(drive->id,
- dma_black_list);
- auide_hwif.drive = drive;
- auide_ddma_init(&auide_hwif);
- dbdma_init_done = 1;
- }
+
+ if( dbdma_init_done == 0 ){
+ auide_hwif.white_list = ide_in_drive_list(drive->id,
+ dma_white_list);
+ auide_hwif.black_list = ide_in_drive_list(drive->id,
+ dma_black_list);
+ auide_hwif.drive = drive;
+ auide_ddma_init(&auide_hwif);
+ dbdma_init_done = 1;
+ }
#endif
- /* Is the drive in our DMA black list? */
- if ( auide_hwif.black_list ) {
- drive->using_dma = 0;
- printk("%s found in dma_blacklist[]! Disabling DMA.\n",
- drive->id->model);
- }
- else
- drive->using_dma = 1;
+ /* Is the drive in our DMA black list? */
+
+ if ( auide_hwif.black_list ) {
+ drive->using_dma = 0;
+
+ /* Borrowed the warning message from ide-dma.c */
- return HWIF(drive)->ide_dma_host_on(drive);
+ printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
+ drive->name, drive->id->model);
+ }
+ else
+ drive->using_dma = 1;
+
+ speed = ide_find_best_mode(drive, XFER_PIO | XFER_MWDMA);
+
+ if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
+ return HWIF(drive)->ide_dma_on(drive);
+
+ return HWIF(drive)->ide_dma_off_quietly(drive);
}
static int auide_dma_test_irq(ide_drive_t *drive)
-{
-// printk("%s\n", __FUNCTION__);
-
- if (!drive->waiting_for_dma)
- printk(KERN_WARNING "%s: ide_dma_test_irq \
+{
+ if (drive->waiting_for_dma == 0)
+ printk(KERN_WARNING "%s: ide_dma_test_irq \
called while not waiting\n", drive->name);
- /* If dbdma didn't execute the STOP command yet, the
- * active bit is still set
+ /* If dbdma didn't execute the STOP command yet, the
+ * active bit is still set
*/
- drive->waiting_for_dma++;
- if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
- printk(KERN_WARNING "%s: timeout waiting for ddma to \
+ drive->waiting_for_dma++;
+ if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
+ printk(KERN_WARNING "%s: timeout waiting for ddma to \
complete\n", drive->name);
- return 1;
- }
- udelay(10);
- return 0;
+ return 1;
+ }
+ udelay(10);
+ return 0;
}
static int auide_dma_host_on(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
- return 0;
+ return 0;
}
static int auide_dma_on(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
- drive->using_dma = 1;
- return auide_dma_host_on(drive);
+ drive->using_dma = 1;
+ return auide_dma_host_on(drive);
}
static int auide_dma_host_off(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
- return 0;
+ return 0;
}
static int auide_dma_off_quietly(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
- drive->using_dma = 0;
- return auide_dma_host_off(drive);
+ drive->using_dma = 0;
+ return auide_dma_host_off(drive);
}
static int auide_dma_lostirq(ide_drive_t *drive)
{
-// printk("%s\n", __FUNCTION__);
-
- printk(KERN_ERR "%s: IRQ lost\n", drive->name);
- return 0;
+ printk(KERN_ERR "%s: IRQ lost\n", drive->name);
+ return 0;
}
static void auide_ddma_tx_callback(int irq, void *param, struct pt_regs *regs)
{
-// printk("%s\n", __FUNCTION__);
-
- _auide_hwif *ahwif = (_auide_hwif*)param;
- ahwif->drive->waiting_for_dma = 0;
- return;
+ _auide_hwif *ahwif = (_auide_hwif*)param;
+ ahwif->drive->waiting_for_dma = 0;
}
static void auide_ddma_rx_callback(int irq, void *param, struct pt_regs *regs)
{
-// printk("%s\n", __FUNCTION__);
+ _auide_hwif *ahwif = (_auide_hwif*)param;
+ ahwif->drive->waiting_for_dma = 0;
+}
+
+#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
- _auide_hwif *ahwif = (_auide_hwif*)param;
- ahwif->drive->waiting_for_dma = 0;
- return;
+static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
+{
+ dev->dev_id = dev_id;
+ dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
+ dev->dev_intlevel = 0;
+ dev->dev_intpolarity = 0;
+ dev->dev_tsize = tsize;
+ dev->dev_devwidth = devwidth;
+ dev->dev_flags = flags;
}
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
static int auide_dma_timeout(ide_drive_t *drive)
{
// printk("%s\n", __FUNCTION__);
- printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
+ printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
- if (HWIF(drive)->ide_dma_test_irq(drive))
- return 0;
+ if (HWIF(drive)->ide_dma_test_irq(drive))
+ return 0;
- return HWIF(drive)->ide_dma_end(drive);
+ return HWIF(drive)->ide_dma_end(drive);
}
-#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
+
+static int auide_ddma_init(_auide_hwif *auide) {
+
+ dbdev_tab_t source_dev_tab, target_dev_tab;
+ u32 dev_id, tsize, devwidth, flags;
+ ide_hwif_t *hwif = auide->hwif;
-static int auide_ddma_init( _auide_hwif *auide )
-{
-// printk("%s\n", __FUNCTION__);
+ dev_id = AU1XXX_ATA_DDMA_REQ;
- dbdev_tab_t source_dev_tab;
-#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
- dbdev_tab_t target_dev_tab;
- ide_hwif_t *hwif = auide->hwif;
- char warning_output [2][80];
- int i;
-#endif
+ if (auide->white_list || auide->black_list) {
+ tsize = 8;
+ devwidth = 32;
+ }
+ else {
+ tsize = 1;
+ devwidth = 16;
+
+ printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
+ printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
+ }
- /* Add our custom device to DDMA device table */
- /* Create our new device entries in the table */
-#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
- source_dev_tab.dev_id = AU1XXX_ATA_DDMA_REQ;
-
- if( auide->white_list || auide->black_list ){
- source_dev_tab.dev_tsize = 8;
- source_dev_tab.dev_devwidth = 32;
- source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
- source_dev_tab.dev_intlevel = 0;
- source_dev_tab.dev_intpolarity = 0;
-
- /* init device table for target - static bus controller - */
- target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
- target_dev_tab.dev_tsize = 8;
- target_dev_tab.dev_devwidth = 32;
- target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
- target_dev_tab.dev_intlevel = 0;
- target_dev_tab.dev_intpolarity = 0;
- target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
- }
- else{
- source_dev_tab.dev_tsize = 1;
- source_dev_tab.dev_devwidth = 16;
- source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
- source_dev_tab.dev_intlevel = 0;
- source_dev_tab.dev_intpolarity = 0;
-
- /* init device table for target - static bus controller - */
- target_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
- target_dev_tab.dev_tsize = 1;
- target_dev_tab.dev_devwidth = 16;
- target_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
- target_dev_tab.dev_intlevel = 0;
- target_dev_tab.dev_intpolarity = 0;
- target_dev_tab.dev_flags = DEV_FLAGS_ANYUSE;
-
- sprintf(&warning_output[0][0],
- "%s is not on ide driver white list.",
- auide_hwif.drive->id->model);
- for ( i=strlen(&warning_output[0][0]) ; i<76; i++ ){
- sprintf(&warning_output[0][i]," ");
- }
-
- sprintf(&warning_output[1][0],
- "To add %s please read 'Documentation/mips/AU1xxx_IDE.README'.",
- auide_hwif.drive->id->model);
- for ( i=strlen(&warning_output[1][0]) ; i<76; i++ ){
- sprintf(&warning_output[1][i]," ");
- }
-
- printk("\n****************************************");
- printk("****************************************\n");
- printk("* %s *\n",&warning_output[0][0]);
- printk("* Switch to safe MWDMA Mode! ");
- printk(" *\n");
- printk("* %s *\n",&warning_output[1][0]);
- printk("****************************************");
- printk("****************************************\n\n");
- }
+#ifdef IDE_AU1XXX_BURSTMODE
+ flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
#else
- source_dev_tab.dev_id = DSCR_CMD0_ALWAYS;
- source_dev_tab.dev_tsize = 8;
- source_dev_tab.dev_devwidth = 32;
- source_dev_tab.dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
- source_dev_tab.dev_intlevel = 0;
- source_dev_tab.dev_intpolarity = 0;
+ flags = DEV_FLAGS_SYNC;
#endif
-#if CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
- /* set flags for tx channel */
- source_dev_tab.dev_flags = DEV_FLAGS_OUT
- | DEV_FLAGS_SYNC
- | DEV_FLAGS_BURSTABLE;
- auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
- /* set flags for rx channel */
- source_dev_tab.dev_flags = DEV_FLAGS_IN
- | DEV_FLAGS_SYNC
- | DEV_FLAGS_BURSTABLE;
- auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+ /* setup dev_tab for tx channel */
+ auide_init_dbdma_dev( &source_dev_tab,
+ dev_id,
+ tsize, devwidth, DEV_FLAGS_OUT | flags);
+ auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+
+ auide_init_dbdma_dev( &source_dev_tab,
+ dev_id,
+ tsize, devwidth, DEV_FLAGS_IN | flags);
+ auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+
+ /* We also need to add a target device for the DMA */
+ auide_init_dbdma_dev( &target_dev_tab,
+ (u32)DSCR_CMD0_ALWAYS,
+ tsize, devwidth, DEV_FLAGS_ANYUSE);
+ auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
+
+ /* Get a channel for TX */
+ auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
+ auide->tx_dev_id,
+ auide_ddma_tx_callback,
+ (void*)auide);
+
+ /* Get a channel for RX */
+ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+ auide->target_dev_id,
+ auide_ddma_rx_callback,
+ (void*)auide);
+
+ auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
+ NUM_DESCRIPTORS);
+ auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
+ NUM_DESCRIPTORS);
+
+ hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
+ PRD_ENTRIES * PRD_BYTES, /* 1 Page */
+ &hwif->dmatable_dma, GFP_KERNEL);
+
+ au1xxx_dbdma_start( auide->tx_chan );
+ au1xxx_dbdma_start( auide->rx_chan );
+
+ return 0;
+}
#else
- /* set flags for tx channel */
- source_dev_tab.dev_flags = DEV_FLAGS_OUT | DEV_FLAGS_SYNC;
- auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
- /* set flags for rx channel */
- source_dev_tab.dev_flags = DEV_FLAGS_IN | DEV_FLAGS_SYNC;
- auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
-#endif
+
+static int auide_ddma_init( _auide_hwif *auide )
+{
+ dbdev_tab_t source_dev_tab;
+ int flags;
-#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
-
- auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
-
- /* Get a channel for TX */
- auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
- auide->tx_dev_id,
- auide_ddma_tx_callback,
- (void*)auide);
- /* Get a channel for RX */
- auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
- auide->target_dev_id,
- auide_ddma_rx_callback,
- (void*)auide);
-#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
- /*
- * Note: if call back is not enabled, update ctp->cur_ptr manually
- */
- auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
- auide->tx_dev_id,
- NULL,
- (void*)auide);
- auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
- DSCR_CMD0_ALWAYS,
- NULL,
- (void*)auide);
+#ifdef IDE_AU1XXX_BURSTMODE
+ flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
+#else
+ flags = DEV_FLAGS_SYNC;
#endif
- auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
- NUM_DESCRIPTORS);
- auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
- NUM_DESCRIPTORS);
-#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
- hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
- PRD_ENTRIES * PRD_BYTES, /* 1 Page */
- &hwif->dmatable_dma, GFP_KERNEL);
-
- auide->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES,
- GFP_KERNEL|GFP_DMA);
- if (auide->sg_table == NULL) {
- return -ENOMEM;
- }
-#endif
- au1xxx_dbdma_start( auide->tx_chan );
- au1xxx_dbdma_start( auide->rx_chan );
- return 0;
+ /* setup dev_tab for tx channel */
+ auide_init_dbdma_dev( &source_dev_tab,
+ (u32)DSCR_CMD0_ALWAYS,
+ 8, 32, DEV_FLAGS_OUT | flags);
+ auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+
+ auide_init_dbdma_dev( &source_dev_tab,
+ (u32)DSCR_CMD0_ALWAYS,
+ 8, 32, DEV_FLAGS_IN | flags);
+ auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
+
+ /* Get a channel for TX */
+ auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
+ auide->tx_dev_id,
+ NULL,
+ (void*)auide);
+
+ /* Get a channel for RX */
+ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
+ DSCR_CMD0_ALWAYS,
+ NULL,
+ (void*)auide);
+
+ auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
+ NUM_DESCRIPTORS);
+ auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
+ NUM_DESCRIPTORS);
+
+ au1xxx_dbdma_start( auide->tx_chan );
+ au1xxx_dbdma_start( auide->rx_chan );
+
+ return 0;
}
+#endif
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
{
- int i;
-#define ide_ioreg_t unsigned long
- ide_ioreg_t *ata_regs = hw->io_ports;
-
- /* fixme */
- for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
- *ata_regs++ = (ide_ioreg_t) ahwif->regbase
- + (ide_ioreg_t)(i << AU1XXX_ATA_REG_OFFSET);
- }
-
- /* set the Alternative Status register */
- *ata_regs = (ide_ioreg_t) ahwif->regbase
- + (ide_ioreg_t)(14 << AU1XXX_ATA_REG_OFFSET);
+ int i;
+ unsigned long *ata_regs = hw->io_ports;
+
+ /* FIXME? */
+ for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
+ *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
+ }
+
+ /* set the Alternative Status register */
+ *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
}
static int au_ide_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
- _auide_hwif *ahwif = &auide_hwif;
- ide_hwif_t *hwif;
+ _auide_hwif *ahwif = &auide_hwif;
+ ide_hwif_t *hwif;
struct resource *res;
int ret = 0;
#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
- char *mode = "MWDMA2";
+ char *mode = "MWDMA2";
#elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
- char *mode = "PIO+DDMA(offload)";
+ char *mode = "PIO+DDMA(offload)";
#endif
- memset(&auide_hwif, 0, sizeof(_auide_hwif));
- auide_hwif.dev = 0;
+ memset(&auide_hwif, 0, sizeof(_auide_hwif));
+ auide_hwif.dev = 0;
ahwif->dev = dev;
ahwif->irq = platform_get_irq(pdev, 0);
goto out;
}
- if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
+ if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
pr_debug("%s: request_mem_region failed\n", DRV_NAME);
- ret = -EBUSY;
+ ret = -EBUSY;
goto out;
- }
+ }
ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
if (ahwif->regbase == 0) {
goto out;
}
- hwif = &ide_hwifs[pdev->id];
+ /* FIXME: This might possibly break PCMCIA IDE devices */
+
+ hwif = &ide_hwifs[pdev->id];
hw_regs_t *hw = &hwif->hw;
- hwif->irq = hw->irq = ahwif->irq;
- hwif->chipset = ide_au1xxx;
+ hwif->irq = hw->irq = ahwif->irq;
+ hwif->chipset = ide_au1xxx;
- auide_setup_ports(hw, ahwif);
+ auide_setup_ports(hw, ahwif);
memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
- hwif->rqsize = CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ;
- hwif->rqsize = ((hwif->rqsize > AU1XXX_ATA_RQSIZE)
- || (hwif->rqsize < 32)) ? AU1XXX_ATA_RQSIZE : hwif->rqsize;
-#else /* if kernel config is not set */
- hwif->rqsize = AU1XXX_ATA_RQSIZE;
-#endif
-
- hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
+ hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
- hwif->swdma_mask = 0x07;
+ hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
+ hwif->swdma_mask = 0x00;
#else
- hwif->mwdma_mask = 0x0;
- hwif->swdma_mask = 0x0;
+ hwif->mwdma_mask = 0x0;
+ hwif->swdma_mask = 0x0;
+#endif
+
+ hwif->noprobe = 0;
+ hwif->drives[0].unmask = 1;
+ hwif->drives[1].unmask = 1;
+
+ /* hold should be on in all cases */
+ hwif->hold = 1;
+ hwif->mmio = 2;
+
+ /* If the user has selected DDMA assisted copies,
+ then set up a few local I/O function entry points
+ */
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
+ hwif->INSW = auide_insw;
+ hwif->OUTSW = auide_outsw;
#endif
- //hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
- hwif->noprobe = 0;
- hwif->drives[0].unmask = 1;
- hwif->drives[1].unmask = 1;
-
- /* hold should be on in all cases */
- hwif->hold = 1;
- hwif->mmio = 2;
-
- /* set up local I/O function entry points */
- hwif->INB = auide_inb;
- hwif->INW = auide_inw;
- hwif->INL = auide_inl;
- hwif->INSW = auide_insw;
- hwif->INSL = auide_insl;
- hwif->OUTB = auide_outb;
- hwif->OUTBSYNC = auide_outbsync;
- hwif->OUTW = auide_outw;
- hwif->OUTL = auide_outl;
- hwif->OUTSW = auide_outsw;
- hwif->OUTSL = auide_outsl;
-
- hwif->tuneproc = &auide_tune_drive;
- hwif->speedproc = &auide_tune_chipset;
+
+ hwif->tuneproc = &auide_tune_drive;
+ hwif->speedproc = &auide_tune_chipset;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- hwif->ide_dma_off_quietly = &auide_dma_off_quietly;
- hwif->ide_dma_timeout = &auide_dma_timeout;
-
- hwif->ide_dma_check = &auide_dma_check;
- hwif->dma_exec_cmd = &auide_dma_exec_cmd;
- hwif->dma_start = &auide_dma_start;
- hwif->ide_dma_end = &auide_dma_end;
- hwif->dma_setup = &auide_dma_setup;
- hwif->ide_dma_test_irq = &auide_dma_test_irq;
- hwif->ide_dma_host_off = &auide_dma_host_off;
- hwif->ide_dma_host_on = &auide_dma_host_on;
- hwif->ide_dma_lostirq = &auide_dma_lostirq;
- hwif->ide_dma_on = &auide_dma_on;
-
- hwif->autodma = 1;
- hwif->drives[0].autodma = hwif->autodma;
- hwif->drives[1].autodma = hwif->autodma;
- hwif->atapi_dma = 1;
- hwif->drives[0].using_dma = 1;
- hwif->drives[1].using_dma = 1;
+ hwif->ide_dma_off_quietly = &auide_dma_off_quietly;
+ hwif->ide_dma_timeout = &auide_dma_timeout;
+
+ hwif->ide_dma_check = &auide_dma_check;
+ hwif->dma_exec_cmd = &auide_dma_exec_cmd;
+ hwif->dma_start = &auide_dma_start;
+ hwif->ide_dma_end = &auide_dma_end;
+ hwif->dma_setup = &auide_dma_setup;
+ hwif->ide_dma_test_irq = &auide_dma_test_irq;
+ hwif->ide_dma_host_off = &auide_dma_host_off;
+ hwif->ide_dma_host_on = &auide_dma_host_on;
+ hwif->ide_dma_lostirq = &auide_dma_lostirq;
+ hwif->ide_dma_on = &auide_dma_on;
+
+ hwif->autodma = 1;
+ hwif->drives[0].autodma = hwif->autodma;
+ hwif->drives[1].autodma = hwif->autodma;
+ hwif->atapi_dma = 1;
+
#else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
- hwif->autodma = 0;
- hwif->channel = 0;
- hwif->hold = 1;
- hwif->select_data = 0; /* no chipset-specific code */
- hwif->config_data = 0; /* no chipset-specific code */
-
- hwif->drives[0].autodma = 0;
- hwif->drives[0].drive_data = 0; /* no drive data */
- hwif->drives[0].using_dma = 0;
- hwif->drives[0].waiting_for_dma = 0;
- hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
- /* secondary hdd not supported */
- hwif->drives[1].autodma = 0;
-
- hwif->drives[1].drive_data = 0;
- hwif->drives[1].using_dma = 0;
- hwif->drives[1].waiting_for_dma = 0;
- hwif->drives[1].autotune = 2; /* 1=autotune, 2=noautotune, 0=default */
-#endif
- hwif->drives[0].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
- hwif->drives[1].io_32bit = 0; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
-
- /*Register Driver with PM Framework*/
-#ifdef CONFIG_PM
- auide_hwif.pm.lock = SPIN_LOCK_UNLOCKED;
- auide_hwif.pm.stopped = 0;
-
- auide_hwif.pm.dev = new_au1xxx_power_device( "ide",
- &au1200ide_pm_callback,
- NULL);
- if ( auide_hwif.pm.dev == NULL )
- printk(KERN_INFO "Unable to create a power management \
- device entry for the au1200-IDE.\n");
- else
- printk(KERN_INFO "Power management device entry for the \
- au1200-IDE loaded.\n");
+ hwif->autodma = 0;
+ hwif->channel = 0;
+ hwif->hold = 1;
+ hwif->select_data = 0; /* no chipset-specific code */
+ hwif->config_data = 0; /* no chipset-specific code */
+
+ hwif->drives[0].autodma = 0;
+ hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
#endif
+ hwif->drives[0].no_io_32bit = 1;
- auide_hwif.hwif = hwif;
- hwif->hwif_data = &auide_hwif;
+ auide_hwif.hwif = hwif;
+ hwif->hwif_data = &auide_hwif;
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
- auide_ddma_init(&auide_hwif);
- dbdma_init_done = 1;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
+ auide_ddma_init(&auide_hwif);
+ dbdma_init_done = 1;
#endif
probe_hwif_init(hwif);
dev_set_drvdata(dev, hwif);
- printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
+ printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
-out:
- return ret;
+ out:
+ return ret;
}
static int au_ide_remove(struct device *dev)
struct platform_device *pdev = to_platform_device(dev);
struct resource *res;
ide_hwif_t *hwif = dev_get_drvdata(dev);
- _auide_hwif *ahwif = &auide_hwif;
+ _auide_hwif *ahwif = &auide_hwif;
ide_unregister(hwif - ide_hwifs);
return driver_register(&au1200_ide_driver);
}
-static void __init au_ide_exit(void)
+static void __exit au_ide_exit(void)
{
driver_unregister(&au1200_ide_driver);
}
-#ifdef CONFIG_PM
-int au1200ide_pm_callback( au1xxx_power_dev_t *dev,\
- au1xxx_request_t request, void *data) {
-
- unsigned int d, err = 0;
- unsigned long flags;
-
- spin_lock_irqsave(auide_hwif.pm.lock, flags);
-
- switch (request){
- case AU1XXX_PM_SLEEP:
- err = au1xxxide_pm_sleep(dev);
- break;
- case AU1XXX_PM_WAKEUP:
- d = *((unsigned int*)data);
- if ( d > 0 && d <= 99) {
- err = au1xxxide_pm_standby(dev);
- }
- else {
- err = au1xxxide_pm_resume(dev);
- }
- break;
- case AU1XXX_PM_GETSTATUS:
- err = au1xxxide_pm_getstatus(dev);
- break;
- case AU1XXX_PM_ACCESS:
- err = au1xxxide_pm_access(dev);
- break;
- case AU1XXX_PM_IDLE:
- err = au1xxxide_pm_idle(dev);
- break;
- case AU1XXX_PM_CLEANUP:
- err = au1xxxide_pm_cleanup(dev);
- break;
- default:
- err = -1;
- break;
- }
-
- spin_unlock_irqrestore(auide_hwif.pm.lock, flags);
-
- return err;
-}
-
-static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev ) {
- return 0;
-}
-
-static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev ) {
-
- int retval;
- ide_hwif_t *hwif = auide_hwif.hwif;
- struct request rq;
- struct request_pm_state rqpm;
- ide_task_t args;
-
- if(auide_hwif.pm.stopped)
- return -1;
-
- /*
- * wait until hard disc is ready
- */
- if ( wait_for_ready(&hwif->drives[0], 35000) ) {
- printk("Wait for drive sleep timeout!\n");
- retval = -1;
- }
-
- /*
- * sequenz to tell the high level ide driver that pm is resuming
- */
- memset(&rq, 0, sizeof(rq));
- memset(&rqpm, 0, sizeof(rqpm));
- memset(&args, 0, sizeof(args));
- rq.flags = REQ_PM_SUSPEND;
- rq.special = &args;
- rq.pm = &rqpm;
- rqpm.pm_step = ide_pm_state_start_suspend;
- rqpm.pm_state = PMSG_SUSPEND;
-
- retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_wait);
-
- if (wait_for_ready (&hwif->drives[0], 35000)) {
- printk("Wait for drive sleep timeout!\n");
- retval = -1;
- }
-
- /*
- * stop dbdma channels
- */
- au1xxx_dbdma_reset(auide_hwif.tx_chan);
- au1xxx_dbdma_reset(auide_hwif.rx_chan);
-
- auide_hwif.pm.stopped = 1;
-
- return retval;
-}
-
-static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev ) {
-
- int retval;
- ide_hwif_t *hwif = auide_hwif.hwif;
- struct request rq;
- struct request_pm_state rqpm;
- ide_task_t args;
-
- if(!auide_hwif.pm.stopped)
- return -1;
-
- /*
- * start dbdma channels
- */
- au1xxx_dbdma_start(auide_hwif.tx_chan);
- au1xxx_dbdma_start(auide_hwif.rx_chan);
-
- /*
- * wait until hard disc is ready
- */
- if (wait_for_ready ( &hwif->drives[0], 35000)) {
- printk("Wait for drive wake up timeout!\n");
- retval = -1;
- }
-
- /*
- * sequenz to tell the high level ide driver that pm is resuming
- */
- memset(&rq, 0, sizeof(rq));
- memset(&rqpm, 0, sizeof(rqpm));
- memset(&args, 0, sizeof(args));
- rq.flags = REQ_PM_RESUME;
- rq.special = &args;
- rq.pm = &rqpm;
- rqpm.pm_step = ide_pm_state_start_resume;
- rqpm.pm_state = PMSG_ON;
-
- retval = ide_do_drive_cmd(&hwif->drives[0], &rq, ide_head_wait);
-
- /*
- * wait for hard disc
- */
- if ( wait_for_ready(&hwif->drives[0], 35000) ) {
- printk("Wait for drive wake up timeout!\n");
- retval = -1;
- }
-
- auide_hwif.pm.stopped = 0;
-
- return retval;
-}
-
-static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev ) {
- return dev->cur_state;
-}
-
-static int au1xxxide_pm_access( au1xxx_power_dev_t *dev ) {
- if (dev->cur_state != AWAKE_STATE)
- return 0;
- else
- return -1;
-}
-
-static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev ) {
- return 0;
-}
-
-static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev ) {
- return 0;
-}
-#endif /* CONFIG_PM */
-
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("AU1200 IDE driver");
ide_hwif_t *hwif;
int h;
+ /*
+ * Find an empty HWIF; if none available, return -ENOMEM.
+ */
for (h = 0; h < MAX_HWIFS; ++h) {
hwif = &ide_hwifs[h];
- /* Find an empty HWIF */
if (hwif->chipset == ide_unknown)
break;
}
+ if (h == MAX_HWIFS) {
+ printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", d->name);
+ return -ENOMEM;
+ }
/* Get the CmdBlk and CtrlBlk Base Registers */
base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
u16 flags;
} via_isa_bridges[] = {
{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
+ { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
},
.driver_data = keymap_acer_aspire_1500
},
- { 0, }
+ { NULL, }
};
static int __init select_keymap(void)
{ { 0x53, 0x02, 0x14 }, 0xf8, 0xf8, 0 },
{ { 0x63, 0x02, 0x0a }, 0xf8, 0xf8, 0 },
{ { 0x63, 0x02, 0x14 }, 0xf8, 0xf8, 0 },
- { { 0x63, 0x02, 0x28 }, 0xf8, 0xf8, 0 },
+ { { 0x63, 0x02, 0x28 }, 0xf8, 0xf8, ALPS_FW_BK_2 }, /* Fujitsu Siemens S6010 */
{ { 0x63, 0x02, 0x3c }, 0x8f, 0x8f, ALPS_WHEEL }, /* Toshiba Satellite S2400-103 */
{ { 0x63, 0x02, 0x50 }, 0xef, 0xef, ALPS_FW_BK_1 }, /* NEC Versa L320 */
{ { 0x63, 0x02, 0x64 }, 0xf8, 0xf8, 0 },
}
dprintk(verbose, DST_CA_DEBUG, 1, " ");
- if (copy_from_user(p_ca_message, (void *)arg, sizeof (struct ca_msg))) {
+ if (copy_from_user(p_ca_message, arg, sizeof (struct ca_msg))) {
result = -EFAULT;
goto free_mem_and_exit;
}
return 0;
}
-static int dst_ca_read(struct file *file, char __user *buffer, size_t length, loff_t *offset)
+static ssize_t dst_ca_read(struct file *file, char __user *buffer, size_t length, loff_t *offset)
{
int bytes_read = 0;
return bytes_read;
}
-static int dst_ca_write(struct file *file, const char __user *buffer, size_t length, loff_t *offset)
+static ssize_t dst_ca_write(struct file *file, const char __user *buffer, size_t length, loff_t *offset)
{
dprintk(verbose, DST_CA_DEBUG, 1, " Device write.");
const size_t imagesize = PAGE_ALIGN(dev->frame_size); /*needs to be page aligned cause the buffers can be mapped individually! */
void *buff = NULL;
u32 i;
- em28xx_coredbg("requested %i buffers with size %i", count, imagesize);
+ em28xx_coredbg("requested %i buffers with size %zd", count, imagesize);
if (count > EM28XX_NUM_FRAMES)
count = EM28XX_NUM_FRAMES;
}
/*
- * Apply power to the MMC stack.
+ * Apply power to the MMC stack. This is a two-stage process.
+ * First, we enable power to the card without the clock running.
+ * We then wait a bit for the power to stabilise. Finally,
+ * enable the bus drivers and clock to the card.
+ *
+ * We must _NOT_ enable the clock prior to power stablising.
+ *
+ * If a host does all the power sequencing itself, ignore the
+ * initial MMC_POWER_UP stage.
*/
static void mmc_power_up(struct mmc_host *host)
{
static int wait_for_msix_trans(nic_t *nic, int i)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u64 val64;
int ret = 0, cnt = 0;
void restore_xmsi_data(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u64 val64;
int i;
static void store_xmsi_data(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u64 val64, addr, data;
int i;
int s2io_enable_msi(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u16 msi_ctrl, msg_val;
struct config_param *config = &nic->config;
struct net_device *dev = nic->dev;
int s2io_enable_msi_x(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u64 tx_mat, rx_mat;
u16 msi_control; /* Temp variable */
int ret, i, j, msix_indx = 1;
}
if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
- netif_stop_queue(dev);
- spin_unlock_irqrestore(&skge->tx_lock, flags);
+ if (!netif_queue_stopped(dev)) {
+ netif_stop_queue(dev);
- printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
- dev->name);
+ printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
+ dev->name);
+ }
+ spin_unlock_irqrestore(&skge->tx_lock, flags);
return NETDEV_TX_BUSY;
}
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.44"
-#define DRV_MODULE_RELDATE "Dec 6, 2005"
+#define DRV_MODULE_VERSION "3.45"
+#define DRV_MODULE_RELDATE "Dec 13, 2005"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
- (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
+ (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
+ (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
+ (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
static void tg3_write_sig_post_reset(struct tg3 *, int);
static int tg3_halt_cpu(struct tg3 *, u32);
+static int tg3_nvram_lock(struct tg3 *);
+static void tg3_nvram_unlock(struct tg3 *);
static int tg3_set_power_state(struct tg3 *tp, int state)
{
tg3_setup_phy(tp, 0);
}
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
+ int i;
+ u32 val;
+
+ for (i = 0; i < 200; i++) {
+ tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
+ if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
+ break;
+ msleep(1);
+ }
+ }
+ tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
+ WOL_DRV_STATE_SHUTDOWN |
+ WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
+
pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
}
}
+ if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
+ !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
+ /* Turn off the PHY */
+ if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
+ tg3_writephy(tp, MII_TG3_EXT_CTRL,
+ MII_TG3_EXT_CTRL_FORCE_LED_OFF);
+ tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
+ tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
+ }
+ }
+
tg3_frob_aux_power(tp);
/* Workaround for unstable PLL clock */
val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
tw32(0x7d00, val);
- if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
+ tg3_nvram_lock(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
+ tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
+ tg3_nvram_unlock(tp);
+ }
}
/* Finally, set the new power state. */
}
}
relink:
- if (current_link_up == 0) {
+ if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
u32 tmp;
tg3_phy_copper_begin(tp);
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
tp->tg3_flags |= TG3_FLAG_NVRAM;
+ tg3_nvram_lock(tp);
tg3_enable_nvram_access(tp);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tg3_get_nvram_size(tp);
tg3_disable_nvram_access(tp);
+ tg3_nvram_unlock(tp);
} else {
tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
if (ret == 0)
*val = swab32(tr32(NVRAM_RDDATA));
- tg3_nvram_unlock(tp);
-
tg3_disable_nvram_access(tp);
+ tg3_nvram_unlock(tp);
+
return ret;
}
offset = offset + (pagesize - page_off);
+ /* Nvram lock released by tg3_nvram_read() above,
+ * so need to get it again.
+ */
+ tg3_nvram_lock(tp);
tg3_enable_nvram_access(tp);
/*
break;
pci_dev_put(peer);
}
- if (!peer || peer == tp->pdev)
- BUG();
+ /* 5704 can be configured in single-port mode, set peer to
+ * tp->pdev in that case.
+ */
+ if (!peer) {
+ peer = tp->pdev;
+ return peer;
+ }
/*
* We don't need to keep the refcount elevated; there's no way
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
+ tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
tg3_full_unlock(tp);
err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
if (err) {
tg3_full_lock(tp, 0);
+ tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
tg3_init_hw(tp);
tp->timer.expires = jiffies + tp->timer_offset;
tg3_full_lock(tp, 0);
+ tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
tg3_init_hw(tp);
tp->timer.expires = jiffies + tp->timer_offset;
#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
+#define NIC_SRAM_WOL_MBOX 0x00000d30
+#define WOL_SIGNATURE 0x474c0000
+#define WOL_DRV_STATE_SHUTDOWN 0x00000001
+#define WOL_DRV_WOL 0x00000002
+#define WOL_SET_MAGIC_PKT 0x00000004
+
#define NIC_SRAM_DATA_CFG_2 0x00000d38
#define SHASTA_EXT_LED_MODE_MASK 0x00018000
#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
+#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
#define MII_TG3_EXT_CTRL_TBI 0x8000
#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
pci-driver.o search.o pci-sysfs.o rom.o setup-res.o
obj-$(CONFIG_PROC_FS) += proc.o
+# Build PCI Express stuff if needed
+obj-$(CONFIG_PCIEPORTBUS) += pcie/
+
obj-$(CONFIG_HOTPLUG) += hotplug.o
# Build the PCI Hotplug drivers if we were asked to
ifeq ($(CONFIG_PCI_DEBUG),y)
EXTRA_CFLAGS += -DDEBUG
endif
-
-# Build PCI Express stuff if needed
-obj-$(CONFIG_PCIEPORTBUS) += pcie/
-
/*
* OS SIMM Cannot be read in other size but a 32bits word.
*/
-static ssize_t jsf_read(struct file * file, char * buf,
+static ssize_t jsf_read(struct file * file, char __user * buf,
size_t togo, loff_t *ppos)
{
unsigned long p = *ppos;
- char *tmp = buf;
+ char __user *tmp = buf;
union byte4 {
char s[4];
return tmp-buf;
}
-static ssize_t jsf_write(struct file * file, const char * buf,
+static ssize_t jsf_write(struct file * file, const char __user * buf,
size_t count, loff_t *ppos)
{
return -ENOSPC;
* Program a block of flash.
* Very simple because we can do it byte by byte anyway.
*/
-static int jsf_ioctl_program(unsigned long arg)
+static int jsf_ioctl_program(void __user *arg)
{
struct jsflash_program_arg abuf;
- char *uptr;
+ char __user *uptr;
unsigned long p;
unsigned int togo;
union {
char s[4];
} b;
- if (copy_from_user(&abuf, (char *)arg, JSFPRGSZ))
+ if (copy_from_user(&abuf, arg, JSFPRGSZ))
return -EFAULT;
p = abuf.off;
togo = abuf.size;
if ((togo & 3) || (p & 3)) return -EINVAL;
- uptr = (char *) (unsigned long) abuf.data;
+ uptr = (char __user *) (unsigned long) abuf.data;
while (togo != 0) {
togo -= 4;
if (copy_from_user(&b.s[0], uptr, 4))
unsigned long arg)
{
int error = -ENOTTY;
+ void __user *argp = (void __user *)arg;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
switch (cmd) {
case JSFLASH_IDENT:
- if (copy_to_user((void *)arg, &jsf0.id, JSFIDSZ))
+ if (copy_to_user(argp, &jsf0.id, JSFIDSZ))
return -EFAULT;
break;
case JSFLASH_ERASE:
error = jsf_ioctl_erase(arg);
break;
case JSFLASH_PROGRAM:
- error = jsf_ioctl_program(arg);
+ error = jsf_ioctl_program(argp);
break;
}
}
}
-void uctrl_get_event_status()
+void uctrl_get_event_status(void)
{
struct uctrl_driver *driver = &drv;
struct uctrl_txn txn;
txn.opcode = READ_EVENT_STATUS;
txn.inbits = 0;
txn.outbits = 2;
- txn.inbuf = 0;
+ txn.inbuf = NULL;
txn.outbuf = outbits;
uctrl_do_txn(&txn);
dprintk(("ev is %x\n", driver->status.event_status));
}
-void uctrl_get_external_status()
+void uctrl_get_external_status(void)
{
struct uctrl_driver *driver = &drv;
struct uctrl_txn txn;
txn.opcode = READ_EXTERNAL_STATUS;
txn.inbits = 0;
txn.outbits = 2;
- txn.inbuf = 0;
+ txn.inbuf = NULL;
txn.outbuf = outbits;
uctrl_do_txn(&txn);
if (driver->irq)
free_irq(driver->irq, driver);
if (driver->regs)
- driver->regs = 0;
+ driver->regs = NULL;
}
module_init(ts102_uctrl_init);
struct vfc_dev {
- volatile struct vfc_regs *regs;
+ volatile struct vfc_regs __iomem *regs;
struct vfc_regs *phys_regs;
unsigned int control_reg;
struct semaphore device_lock_sem;
}
printk("Initializing vfc%d\n",instance);
dev->regs = NULL;
- dev->regs = (volatile struct vfc_regs *)
+ dev->regs = (volatile struct vfc_regs __iomem *)
sbus_ioremap(&sdev->resource[0], 0,
sizeof(struct vfc_regs), vfcstr);
dev->which_io = sdev->reg_addrs[0].which_io;
int timeout = 1000;
while (!timeout--) {
- if (dev->regs->control & VFC_STATUS_CAPTURE)
+ if (sbus_readl(&dev->regs->control) & VFC_STATUS_CAPTURE)
break;
vfc_i2c_delay_no_busy(dev, 100);
}
if(dev == NULL)
return;
devfs_remove("vfc/%d", dev->instance);
- sbus_iounmap((unsigned long)dev->regs, sizeof(struct vfc_regs));
+ sbus_iounmap(dev->regs, sizeof(struct vfc_regs));
kfree(dev);
}
void ibmvscsi_release_crq_queue(struct crq_queue *queue,
struct ibmvscsi_host_data *hostdata,
int max_requests);
-void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+int ibmvscsi_reset_crq_queue(struct crq_queue *queue,
struct ibmvscsi_host_data *hostdata);
void ibmvscsi_handle_crq(struct viosrp_crq *crq,
*
* no-op for iSeries
*/
-void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+int ibmvscsi_reset_crq_queue(struct crq_queue *queue,
struct ibmvscsi_host_data *hostdata)
{
+ return 0;
}
/**
rc = plpar_hcall_norets(H_REG_CRQ,
vdev->unit_address,
queue->msg_token, PAGE_SIZE);
+ if (rc == H_Resource)
+ /* maybe kexecing and resource is busy. try a reset */
+ rc = ibmvscsi_reset_crq_queue(queue,
+ hostdata);
+
if (rc == 2) {
/* Adapter is good, but other end is not ready */
printk(KERN_WARNING "ibmvscsi: Partner adapter not ready\n");
* @hostdata: ibmvscsi_host_data of host
*
*/
-void ibmvscsi_reset_crq_queue(struct crq_queue *queue,
+int ibmvscsi_reset_crq_queue(struct crq_queue *queue,
struct ibmvscsi_host_data *hostdata)
{
int rc;
printk(KERN_WARNING
"ibmvscsi: couldn't register crq--rc 0x%x\n", rc);
}
+ return rc;
}
switch(param) {
case ISCSI_PARAM_MAX_RECV_DLENGTH: {
char *saveptr = conn->data;
- int flags = GFP_KERNEL;
+ gfp_t flags = GFP_KERNEL;
if (conn->data_size >= value) {
conn->max_recv_dlength = value;
struct scatterlist *psg = &qc->pad_sgent;
void *addr = kmap_atomic(psg->page, KM_IRQ0);
memcpy(addr + psg->offset, pad_buf, qc->pad_len);
- kunmap_atomic(psg->page, KM_IRQ0);
+ kunmap_atomic(addr, KM_IRQ0);
}
} else {
if (sg_dma_len(&sg[0]) > 0)
if (qc->tf.flags & ATA_TFLAG_WRITE) {
void *addr = kmap_atomic(psg->page, KM_IRQ0);
memcpy(pad_buf, addr + psg->offset, qc->pad_len);
- kunmap_atomic(psg->page, KM_IRQ0);
+ kunmap_atomic(addr, KM_IRQ0);
}
sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
if (unlikely(!ata_dev_present(dev)))
return NULL;
- if (!atapi_enabled) {
- if (unlikely(dev->class == ATA_DEV_ATAPI))
+ if (!atapi_enabled || (ap->flags & ATA_FLAG_NO_ATAPI)) {
+ if (unlikely(dev->class == ATA_DEV_ATAPI)) {
+ printk(KERN_WARNING "ata%u(%u): WARNING: ATAPI is %s, device ignored.\n",
+ ap->id, dev->devno, atapi_enabled ? "not supported with this driver" : "disabled");
return NULL;
+ }
}
return dev;
sg->offset;
} else
buf = cmd->request_buffer;
- memset(cmd->request_buffer, 0, cmd->cmnd[4]);
+ memset(buf, 0, cmd->cmnd[4]);
if (cmd->use_sg) {
struct scatterlist *sg;
*/
#define LOOP_TRANSITION(ha) \
(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
- test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
-
-#define LOOP_NOT_READY(ha) \
- ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
- test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
- test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
- test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
+ test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
atomic_read(&ha->loop_state) == LOOP_DOWN)
-#define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
-
#define TGT_Q(ha, t) (ha->otgt[t])
#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
rval = qla2x00_get_adapter_id(ha,
&loop_id, &al_pa, &area, &domain, &topo);
if (rval != QLA_SUCCESS) {
- if (LOOP_NOT_READY(ha) || atomic_read(&ha->loop_down_timer) ||
+ if (LOOP_TRANSITION(ha) || atomic_read(&ha->loop_down_timer) ||
(rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
DEBUG2(printk("%s(%ld) Loop is in a transition state\n",
__func__, ha->host_no));
}
if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
- if (LOOP_NOT_READY(ha)) {
+ if (LOOP_TRANSITION(ha)) {
rval = QLA_FUNCTION_FAILED;
} else {
rval = qla2x00_configure_fabric(ha);
if (qla2x00_is_reserved_id(ha, loop_id))
continue;
- if (atomic_read(&ha->loop_down_timer) || LOOP_NOT_READY(ha))
+ if (atomic_read(&ha->loop_down_timer) || LOOP_TRANSITION(ha))
break;
if (swl != NULL) {
resid = resid_len;
cp->resid = resid;
CMD_RESID_LEN(cp) = resid;
+
+ if (!lscsi_status &&
+ ((unsigned)(cp->request_bufflen - resid) <
+ cp->underflow)) {
+ qla_printk(KERN_INFO, ha,
+ "scsi(%ld:%d:%d:%d): Mid-layer underflow "
+ "detected (%x of %x bytes)...returning "
+ "error status.\n", ha->host_no,
+ cp->device->channel, cp->device->id,
+ cp->device->lun, resid,
+ cp->request_bufflen);
+
+ cp->result = DID_ERROR << 16;
+ break;
+ }
}
cp->result = DID_OK << 16 | lscsi_status;
MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
+ ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
+ ATA_FLAG_NO_ATAPI),
MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
CRQB_FLAG_READ = (1 << 0),
PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
PDC_RESET = (1 << 11), /* HDMA reset */
+
+ PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
+ ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
};
/* board_2037x */
{
.sht = &pdc_ata_sht,
- .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_SRST | ATA_FLAG_MMIO,
+ .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
/* board_20319 */
{
.sht = &pdc_ata_sht,
- .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_SRST | ATA_FLAG_MMIO,
+ .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
/* board_20619 */
{
.sht = &pdc_ata_sht,
- .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
- ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
+ .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
{
.sht = &pdc_sata_sht,
.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
- ATA_FLAG_SRST | ATA_FLAG_MMIO,
+ ATA_FLAG_SRST | ATA_FLAG_MMIO |
+ ATA_FLAG_NO_ATAPI,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
**/
static void scsi_eh_done(struct scsi_cmnd *scmd)
{
+ struct completion *eh_action;
+
SCSI_LOG_ERROR_RECOVERY(3,
printk("%s scmd: %p result: %x\n",
__FUNCTION__, scmd, scmd->result));
- complete(scmd->device->host->eh_action);
+
+ eh_action = scmd->device->host->eh_action;
+ if (eh_action)
+ complete(eh_action);
}
/**
scsi_io_completion(cmd, cmd->result == 0 ? cmd->bufflen : 0, 0);
}
+void scsi_setup_blk_pc_cmnd(struct scsi_cmnd *cmd, int retries)
+{
+ struct request *req = cmd->request;
+
+ BUG_ON(sizeof(req->cmd) > sizeof(cmd->cmnd));
+ memcpy(cmd->cmnd, req->cmd, sizeof(cmd->cmnd));
+ cmd->cmd_len = req->cmd_len;
+ if (!req->data_len)
+ cmd->sc_data_direction = DMA_NONE;
+ else if (rq_data_dir(req) == WRITE)
+ cmd->sc_data_direction = DMA_TO_DEVICE;
+ else
+ cmd->sc_data_direction = DMA_FROM_DEVICE;
+
+ cmd->transfersize = req->data_len;
+ cmd->allowed = retries;
+ cmd->timeout_per_command = req->timeout;
+}
+EXPORT_SYMBOL_GPL(scsi_setup_blk_pc_cmnd);
+
static int scsi_prep_fn(struct request_queue *q, struct request *req)
{
struct scsi_device *sdev = q->queuedata;
goto kill;
}
} else {
- memcpy(cmd->cmnd, req->cmd, sizeof(cmd->cmnd));
- cmd->cmd_len = req->cmd_len;
- if (rq_data_dir(req) == WRITE)
- cmd->sc_data_direction = DMA_TO_DEVICE;
- else if (req->data_len)
- cmd->sc_data_direction = DMA_FROM_DEVICE;
- else
- cmd->sc_data_direction = DMA_NONE;
-
- cmd->transfersize = req->data_len;
- cmd->allowed = 3;
- cmd->timeout_per_command = req->timeout;
+ scsi_setup_blk_pc_cmnd(cmd, 3);
cmd->done = scsi_generic_done;
}
}
}
static void*
-mempool_zone_alloc_skb(unsigned int gfp_mask, void *pool_data)
+mempool_zone_alloc_skb(gfp_t gfp_mask, void *pool_data)
{
struct mempool_zone *zone = pool_data;
* SG_IO from block layer already setup, just copy cdb basically
*/
if (blk_pc_request(rq)) {
- if (sizeof(rq->cmd) > sizeof(SCpnt->cmnd))
- return 0;
-
- memcpy(SCpnt->cmnd, rq->cmd, sizeof(SCpnt->cmnd));
- SCpnt->cmd_len = rq->cmd_len;
- if (rq_data_dir(rq) == WRITE)
- SCpnt->sc_data_direction = DMA_TO_DEVICE;
- else if (rq->data_len)
- SCpnt->sc_data_direction = DMA_FROM_DEVICE;
- else
- SCpnt->sc_data_direction = DMA_NONE;
-
- this_count = rq->data_len;
+ scsi_setup_blk_pc_cmnd(SCpnt, SD_PASSTHROUGH_RETRIES);
if (rq->timeout)
timeout = rq->timeout;
- SCpnt->transfersize = rq->data_len;
- SCpnt->allowed = SD_PASSTHROUGH_RETRIES;
goto queue;
}
* these are already setup, just copy cdb basically
*/
if (SCpnt->request->flags & REQ_BLOCK_PC) {
- struct request *rq = SCpnt->request;
+ scsi_setup_blk_pc_cmnd(SCpnt, MAX_RETRIES);
- if (sizeof(rq->cmd) > sizeof(SCpnt->cmnd))
- return 0;
-
- memcpy(SCpnt->cmnd, rq->cmd, sizeof(SCpnt->cmnd));
- SCpnt->cmd_len = rq->cmd_len;
- if (!rq->data_len)
- SCpnt->sc_data_direction = DMA_NONE;
- else if (rq_data_dir(rq) == WRITE)
- SCpnt->sc_data_direction = DMA_TO_DEVICE;
- else
- SCpnt->sc_data_direction = DMA_FROM_DEVICE;
-
- this_count = rq->data_len;
- if (rq->timeout)
- timeout = rq->timeout;
+ if (SCpnt->timeout_per_command)
+ timeout = SCpnt->timeout_per_command;
- SCpnt->transfersize = rq->data_len;
goto queue;
}
*/
static int st_init_command(struct scsi_cmnd *SCpnt)
{
- struct request *rq;
-
if (!(SCpnt->request->flags & REQ_BLOCK_PC))
return 0;
- rq = SCpnt->request;
- if (sizeof(rq->cmd) > sizeof(SCpnt->cmnd))
- return 0;
-
- memcpy(SCpnt->cmnd, rq->cmd, sizeof(SCpnt->cmnd));
- SCpnt->cmd_len = rq->cmd_len;
-
- if (rq_data_dir(rq) == WRITE)
- SCpnt->sc_data_direction = DMA_TO_DEVICE;
- else if (rq->data_len)
- SCpnt->sc_data_direction = DMA_FROM_DEVICE;
- else
- SCpnt->sc_data_direction = DMA_NONE;
-
- SCpnt->timeout_per_command = rq->timeout;
- SCpnt->transfersize = rq->data_len;
+ scsi_setup_blk_pc_cmnd(SCpnt, 0);
SCpnt->done = st_intr;
return 1;
}
goal->iu = 0;
goal->dt = 0;
goal->qas = 0;
- goal->period = 0;
goal->offset = 0;
return;
}
* Many devices implement PPR in a buggy way, so only use it if we
* really want to.
*/
- if (goal->iu || goal->dt || goal->qas || (goal->period < 0xa)) {
+ if (goal->offset &&
+ (goal->iu || goal->dt || goal->qas || (goal->period < 0xa))) {
nego = NS_PPR;
} else if (spi_width(starget) != goal->width) {
nego = NS_WIDE;
* at the source, so we must turn off PIRQ.
*/
pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
+ mb();
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
uhci->hc_inaccessible = 1;
hcd->poll_rh = 0;
* really don't want to keep a stale HCD_FLAG_HW_ACCESSIBLE=0
*/
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+ mb();
if (uhci->rh_state == UHCI_RH_RESET) /* Dead */
return 0;
size = ((report->size - 1) >> 3) + 1;
- if (len < size)
+ if (len < size) {
dbg("report %d is too short, (%d < %d)", report->id, len, size);
+ memset(data + len, 0, size - len);
+ }
if (hid->claimed & HID_CLAIMED_HIDDEV)
hiddev_report_event(hid, report);
int ret;
wait_queue_t wait;
- dbg ("auerchar_write %d bytes", len);
+ dbg ("auerchar_write %zd bytes", len);
/* Error checking */
if (!ccp)
* the fb. it's inefficient for them to do anything less than 64*8
* writes since we update the lcd in each write() anyway.
*/
-static ssize_t arcfb_write(struct file *file, const char *buf, size_t count,
+static ssize_t arcfb_write(struct file *file, const char __user *buf, size_t count,
loff_t *ppos)
{
/* modded from epson 1355 */
int const shift = dst_idx-src_idx;
int left, right;
- first = ~0UL >> dst_idx;
- last = ~(~0UL >> ((dst_idx+n) % bits));
+ first = FB_SHIFT_HIGH(~0UL, dst_idx);
+ last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits));
if (!shift) {
// Same alignment for source and dest
shift = dst_idx-src_idx;
- first = ~0UL << (bits - 1 - dst_idx);
- last = ~(~0UL << (bits - 1 - ((dst_idx-n) % bits)));
+ first = FB_SHIFT_LOW(~0UL, bits - 1 - dst_idx);
+ last = ~(FB_SHIFT_LOW(~0UL, bits - 1 - ((dst_idx-n) % bits)));
if (!shift) {
// Same alignment for source and dest
if (!n)
return;
- first = ~0UL >> dst_idx;
- last = ~(~0UL >> ((dst_idx+n) % bits));
+ first = FB_SHIFT_HIGH(~0UL, dst_idx);
+ last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
if (!n)
return;
- first = ~0UL >> dst_idx;
- last = ~(~0UL >> ((dst_idx+n) % bits));
+ first = FB_SHIFT_HIGH(~0UL, dst_idx);
+ last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
if (!n)
return;
- first = ~0UL >> dst_idx;
- last = ~(~0UL >> ((dst_idx+n) % bits));
+ first = FB_SHIFT_HIGH(~0UL, dst_idx);
+ last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
if (!n)
return;
- first = ~0UL >> dst_idx;
- last = ~(~0UL >> ((dst_idx+n) % bits));
+ first = FB_SHIFT_HIGH(~0UL, dst_idx);
+ last = ~(FB_SHIFT_HIGH(~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
#define FB_WRITEL fb_writel
#define FB_READL fb_readl
-#if defined (__BIG_ENDIAN)
-#define LEFT_POS(bpp) (32 - bpp)
-#define SHIFT_HIGH(val, bits) ((val) >> (bits))
-#define SHIFT_LOW(val, bits) ((val) << (bits))
-#define BIT_NR(b) (7 - (b))
-#else
-#define LEFT_POS(bpp) (0)
-#define SHIFT_HIGH(val, bits) ((val) << (bits))
-#define SHIFT_LOW(val, bits) ((val) >> (bits))
-#define BIT_NR(b) (b)
-#endif
-
static inline void color_imageblit(const struct fb_image *image,
struct fb_info *p, u8 __iomem *dst1,
u32 start_index,
val = 0;
if (start_index) {
- u32 start_mask = ~(SHIFT_HIGH(~(u32)0, start_index));
+ u32 start_mask = ~(FB_SHIFT_HIGH(~(u32)0, start_index));
val = FB_READL(dst) & start_mask;
shift = start_index;
}
color = palette[*src];
else
color = *src;
- color <<= LEFT_POS(bpp);
- val |= SHIFT_HIGH(color, shift);
+ color <<= FB_LEFT_POS(bpp);
+ val |= FB_SHIFT_HIGH(color, shift);
if (shift >= null_bits) {
FB_WRITEL(val, dst++);
val = (shift == null_bits) ? 0 :
- SHIFT_LOW(color, 32 - shift);
+ FB_SHIFT_LOW(color, 32 - shift);
}
shift += bpp;
shift &= (32 - 1);
src++;
}
if (shift) {
- u32 end_mask = SHIFT_HIGH(~(u32)0, shift);
+ u32 end_mask = FB_SHIFT_HIGH(~(u32)0, shift);
FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
}
u32 i, j, l;
dst2 = (u32 __iomem *) dst1;
+ fgcolor <<= FB_LEFT_POS(bpp);
+ bgcolor <<= FB_LEFT_POS(bpp);
for (i = image->height; i--; ) {
shift = val = 0;
/* write leading bits */
if (start_index) {
- u32 start_mask = ~(SHIFT_HIGH(~(u32)0, start_index));
+ u32 start_mask = ~(FB_SHIFT_HIGH(~(u32)0,start_index));
val = FB_READL(dst) & start_mask;
shift = start_index;
}
while (j--) {
l--;
- color = (*s & 1 << (BIT_NR(l))) ? fgcolor : bgcolor;
- color <<= LEFT_POS(bpp);
- val |= SHIFT_HIGH(color, shift);
+ color = (*s & 1 << (FB_BIT_NR(l))) ? fgcolor : bgcolor;
+ val |= FB_SHIFT_HIGH(color, shift);
/* Did the bitshift spill bits to the next long? */
if (shift >= null_bits) {
FB_WRITEL(val, dst++);
val = (shift == null_bits) ? 0 :
- SHIFT_LOW(color,32 - shift);
+ FB_SHIFT_LOW(color,32 - shift);
}
shift += bpp;
shift &= (32 - 1);
/* write trailing bits */
if (shift) {
- u32 end_mask = SHIFT_HIGH(~(u32)0, shift);
+ u32 end_mask = FB_SHIFT_HIGH(~(u32)0, shift);
FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
}
struct fbcon_ops *ops;
struct display *p = &fb_display[vc->vc_num];
struct fb_var_screeninfo var;
- int i, prev_console;
+ int i, prev_console, charcnt = 256;
info = registered_fb[con2fb_map[vc->vc_num]];
ops = info->fbcon_par;
fb_set_var(info, &var);
ops->var = info->var;
- if (old_info != NULL && old_info != info) {
+ if (old_info != NULL && (old_info != info ||
+ info->flags & FBINFO_MISC_ALWAYS_SETPAR)) {
if (info->fbops->fb_set_par)
info->fbops->fb_set_par(info);
fbcon_del_cursor_timer(old_info);
vc->vc_can_do_color = (fb_get_color_depth(&info->var, &info->fix)!=1);
vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;
+
+ if (p->userfont)
+ charcnt = FNTCHARCNT(vc->vc_font.data);
+
+ if (charcnt > 256)
+ vc->vc_complement_mask <<= 1;
+
updatescrollmode(p, info, vc);
switch (p->scrollmode) {
scrollback_max = 0;
scrollback_current = 0;
- ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
- ops->update_start(info);
+
+ if (!fbcon_is_inactive(vc, info)) {
+ ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
+ ops->update_start(info);
+ }
+
fbcon_set_palette(vc, color_table);
fbcon_clear_margins(vc, 0);
ops->graphics = 1;
if (!blank) {
+ if (info->fbops->fb_save_state)
+ info->fbops->fb_save_state(info);
var.activate = FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
fb_set_var(info, &var);
ops->graphics = 0;
ops->var = info->var;
- }
+ } else if (info->fbops->fb_restore_state)
+ info->fbops->fb_restore_state(info);
}
if (!fbcon_is_inactive(vc, info)) {
updatescrollmode(p, info, vc);
scrollback_max = 0;
scrollback_current = 0;
- ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
- ops->update_start(info);
+
+ if (!fbcon_is_inactive(vc, info)) {
+ ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
+ ops->update_start(info);
+ }
+
fbcon_set_palette(vc, color_table);
update_screen(vc);
if (softback_buf)
updatescrollmode(p, info, vc);
scrollback_max = 0;
scrollback_current = 0;
- ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
- ops->update_start(info);
+
+ if (!fbcon_is_inactive(vc, info)) {
+ ops->var.xoffset = ops->var.yoffset =
+ p->yscroll = 0;
+ ops->update_start(info);
+ }
+
fbcon_set_palette(vc, color_table);
update_screen(vc);
if (softback_buf)
* I/O cycles storing into a reserved memory space at
* physical address 0x3000000
*/
- unsigned char *iop;
+ unsigned char __iomem *iop;
iop = ioremap(0x3000000, 0x5000);
if (iop == NULL) {
writeb(EXT_BIU_MISC, iop + 0x3ce);
writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
- iounmap((void *)iop);
+ iounmap(iop);
#else
/*
* Most other machine types are "normal", so
int
fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
{
+ struct fb_fix_screeninfo *fix = &info->fix;
int xoffset = var->xoffset;
int yoffset = var->yoffset;
- int err;
+ int err = 0, yres = info->var.yres;
+
+ if (var->yoffset > 0) {
+ if (var->vmode & FB_VMODE_YWRAP) {
+ if (!fix->ywrapstep || (var->yoffset % fix->ywrapstep))
+ err = -EINVAL;
+ else
+ yres = 0;
+ } else if (!fix->ypanstep || (var->yoffset % fix->ypanstep))
+ err = -EINVAL;
+ }
+
+ if (var->xoffset > 0 && (!fix->xpanstep ||
+ (var->xoffset % fix->xpanstep)))
+ err = -EINVAL;
+
+ if (err || !info->fbops->fb_pan_display || xoffset < 0 ||
+ yoffset < 0 || var->yoffset + yres > info->var.yres_virtual ||
+ var->xoffset + info->var.xres > info->var.xres_virtual)
+ return -EINVAL;
- if (xoffset < 0 || yoffset < 0 || !info->fbops->fb_pan_display ||
- xoffset + info->var.xres > info->var.xres_virtual ||
- yoffset + info->var.yres > info->var.yres_virtual)
- return -EINVAL;
if ((err = info->fbops->fb_pan_display(var, info)))
return err;
info->var.xoffset = var->xoffset;
int __devinit pxafb_setup(char *options)
{
# ifdef CONFIG_FB_PXA_PARAMETERS
- strlcpy(g_options, options, sizeof(g_options));
+ if (options)
+ strlcpy(g_options, options, sizeof(g_options));
# endif
return 0;
}
JOURNAL_PER_BALANCE_CNT * 2 +
2 * REISERFS_QUOTA_INIT_BLOCKS(inode->i_sb);
struct reiserfs_transaction_handle th;
+ int err;
truncate_inode_pages(&inode->i_data, 0);
}
reiserfs_update_inode_transaction(inode);
- if (reiserfs_delete_object(&th, inode)) {
- up(&inode->i_sem);
- goto out;
- }
+ err = reiserfs_delete_object(&th, inode);
/* Do quota update inside a transaction for journaled quotas. We must do that
* after delete_object so that quota updates go into the same transaction as
* stat data deletion */
- DQUOT_FREE_INODE(inode);
+ if (!err)
+ DQUOT_FREE_INODE(inode);
if (journal_end(&th, inode->i_sb, jbegin_count)) {
up(&inode->i_sem);
up(&inode->i_sem);
+ /* check return value from reiserfs_delete_object after
+ * ending the transaction
+ */
+ if (err)
+ goto out;
+
/* all items of file are deleted, so we can remove "save" link */
remove_save_link(inode, 0 /* not truncate */ ); /* we can't do anything
* about an error here */
struct page *page = NULL;
int error;
struct buffer_head *bh = NULL;
+ int err2;
reiserfs_write_lock(p_s_inode->i_sb);
transaction of truncating gets committed - on reboot the file
either appears truncated properly or not truncated at all */
add_save_link(&th, p_s_inode, 1);
- error = reiserfs_do_truncate(&th, p_s_inode, page, update_timestamps);
- if (error)
- goto out;
+ err2 = reiserfs_do_truncate(&th, p_s_inode, page, update_timestamps);
error =
journal_end(&th, p_s_inode->i_sb, JOURNAL_PER_BALANCE_CNT * 2 + 1);
if (error)
goto out;
+ /* check reiserfs_do_truncate after ending the transaction */
+ if (err2) {
+ error = err2;
+ goto out;
+ }
+
if (update_timestamps) {
error = remove_save_link(p_s_inode, 1 /* truncate */ );
if (error)
}
atomic_dec(&journal->j_async_throttle);
+ /* We're skipping the commit if there's an error */
+ if (retval || reiserfs_is_journal_aborted(journal))
+ barrier = 0;
+
/* wait on everything written so far before writing the commit
* if we are in barrier mode, send the commit down now
*/
BUG_ON(atomic_read(&(jl->j_commit_left)) != 1);
if (!barrier) {
- if (buffer_dirty(jl->j_commit_bh))
- BUG();
- mark_buffer_dirty(jl->j_commit_bh);
- sync_dirty_buffer(jl->j_commit_bh);
+ /* If there was a write error in the journal - we can't commit
+ * this transaction - it will be invalid and, if successful,
+ * will just end up propogating the write error out to
+ * the file system. */
+ if (likely(!retval && !reiserfs_is_journal_aborted (journal))) {
+ if (buffer_dirty(jl->j_commit_bh))
+ BUG();
+ mark_buffer_dirty(jl->j_commit_bh) ;
+ sync_dirty_buffer(jl->j_commit_bh) ;
+ }
} else
wait_on_buffer(jl->j_commit_bh);
STATIC int xfs_qm_init_quotainos(xfs_mount_t *);
STATIC int xfs_qm_init_quotainfo(xfs_mount_t *);
-STATIC int xfs_qm_shake(int, unsigned int);
+STATIC int xfs_qm_shake(int, gfp_t);
#ifdef DEBUG
extern mutex_t qcheck_lock;
*/
/* ARGSUSED */
STATIC int
-xfs_qm_shake(int nr_to_scan, unsigned int gfp_mask)
+xfs_qm_shake(int nr_to_scan, gfp_t gfp_mask)
{
int ndqused, nfree, n;
#define R_ARM_NONE 0
#define R_ARM_PC24 1
#define R_ARM_ABS32 2
+#define R_ARM_CALL 28
+#define R_ARM_JUMP24 29
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct sal_log_record_header {
u64 id; /* Unique monotonically increasing ID */
sal_log_revision_t revision; /* Major and Minor revision of header */
- u16 severity; /* Error Severity */
+ u8 severity; /* Error Severity */
+ u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
u32 len; /* Length of this error log in bytes */
sal_log_timestamp_t timestamp; /* Timestamp */
efi_guid_t platform_guid; /* Unique OEM Platform ID */
u8 white_list, black_list;
struct dbdma_cmd *dma_table_cpu;
dma_addr_t dma_table_dma;
- struct scatterlist *sg_table;
- int sg_nents;
- int sg_dma_direction;
#endif
struct device *dev;
int irq;
} _auide_hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-struct drive_list_entry {
- const char * id_model;
- const char * id_firmware;
-};
-
/* HD white list */
static const struct drive_list_entry dma_white_list [] = {
/*
* Multi-Word DMA + DbDMA functions
*/
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-
- static int in_drive_list(struct hd_driveid *id,
- const struct drive_list_entry *drive_table);
static int auide_build_sglist(ide_drive_t *drive, struct request *rq);
static int auide_build_dmatable(ide_drive_t *drive);
static int auide_dma_end(ide_drive_t *drive);
- static void auide_dma_start(ide_drive_t *drive );
ide_startstop_t auide_dma_intr (ide_drive_t *drive);
static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
static int auide_dma_setup(ide_drive_t *drive);
static void auide_ddma_rx_callback(int irq, void *param,
struct pt_regs *regs);
static int auide_dma_off_quietly(ide_drive_t *drive);
- static int auide_dma_timeout(ide_drive_t *drive);
-
#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
/*******************************************************************************
#define SBC_IDE_MDMA2_TPM (0x00<<6)
#define SBC_IDE_MDMA2_TA (0x12<<0)
+#define SBC_IDE_TIMING(mode) \
+ SBC_IDE_##mode##_TWCS | \
+ SBC_IDE_##mode##_TCSH | \
+ SBC_IDE_##mode##_TCSOFF | \
+ SBC_IDE_##mode##_TWP | \
+ SBC_IDE_##mode##_TCSW | \
+ SBC_IDE_##mode##_TPM | \
+ SBC_IDE_##mode##_TA
/* Memory parity error register with associated bit constants. */
#ifndef __ASSEMBLY__
-extern __volatile__ unsigned long *sun4c_memerr_reg;
+extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
#endif
#define SUN4C_MPE_ERROR 0x80 /* Parity error detected. (ro) */
#include <asm/pbm.h>
struct linux_pcic {
- void * __iomem pcic_regs;
+ void __iomem *pcic_regs;
unsigned long pcic_io;
- void * __iomem pcic_config_space_addr;
- void * __iomem pcic_config_space_data;
+ void __iomem *pcic_config_space_addr;
+ void __iomem *pcic_config_space_data;
struct resource pcic_res_regs;
struct resource pcic_res_io;
struct resource pcic_res_cfg_addr;
/* perform fb specific mmap */
int (*fb_mmap)(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
+
+ /* save current hardware state */
+ void (*fb_save_state)(struct fb_info *info);
+
+ /* restore saved state */
+ void (*fb_restore_state)(struct fb_info *info);
};
#ifdef CONFIG_FB_TILEBLITTING
from userspace */
#define FBINFO_MISC_TILEBLITTING 0x20000 /* use tile blitting */
+/* A driver may set this flag to indicate that it does want a set_par to be
+ * called every time when fbcon_switch is executed. The advantage is that with
+ * this flag set you can really be shure that set_par is always called before
+ * any of the functions dependant on the correct hardware state or altering
+ * that state, even if you are using some broken X releases. The disadvantage
+ * is that it introduces unwanted delays to every console switch if set_par
+ * is slow. It is a good idea to try this flag in the drivers initialization
+ * code whenever there is a bug report related to switching between X and the
+ * framebuffer console.
+ */
+#define FBINFO_MISC_ALWAYS_SETPAR 0x40000
+
struct fb_info {
int node;
int flags;
#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
#define fb_memset memset
+#endif
+
+#if defined (__BIG_ENDIAN)
+#define FB_LEFT_POS(bpp) (32 - bpp)
+#define FB_SHIFT_HIGH(val, bits) ((val) >> (bits))
+#define FB_SHIFT_LOW(val, bits) ((val) << (bits))
+#define FB_BIT_NR(b) (7 - (b))
+#else
+#define FB_LEFT_POS(bpp) (0)
+#define FB_SHIFT_HIGH(val, bits) ((val) << (bits))
+#define FB_SHIFT_LOW(val, bits) ((val) >> (bits))
+#define FB_BIT_NR(b) (b)
#endif
/*
#include <asm/io.h>
#include <asm/semaphore.h>
-/*
- * This is the multiple IDE interface driver, as evolved from hd.c.
- * It supports up to four IDE interfaces, on one or more IRQs (usually 14 & 15).
- * There can be up to two drives per interface, as per the ATA-2 spec.
- *
- * Primary i/f: ide0: major=3; (hda) minor=0; (hdb) minor=64
- * Secondary i/f: ide1: major=22; (hdc or hd1a) minor=0; (hdd or hd1b) minor=64
- * Tertiary i/f: ide2: major=33; (hde) minor=0; (hdf) minor=64
- * Quaternary i/f: ide3: major=34; (hdg) minor=0; (hdh) minor=64
- */
-
/******************************************************************************
* IDE driver configuration options (play with these as desired):
*
#define WAIT_CMD (10*HZ) /* 10sec - maximum wait for an IRQ to happen */
#define WAIT_MIN_SLEEP (2*HZ/100) /* 20msec - minimum sleep time */
-#define HOST(hwif,chipset) \
-{ \
- return ((hwif)->chipset == chipset) ? 1 : 0; \
-}
-
/*
* Check for an interrupt and acknowledge the interrupt status
*/
} b;
} ata_nsector_t, ata_data_t, atapi_bcount_t, ata_index_t;
-/*
- * ATA-IDE Error Register
- *
- * mark : Bad address mark
- * tzero : Couldn't find track 0
- * abrt : Aborted Command
- * mcr : Media Change Request
- * id : ID field not found
- * mce : Media Change Event
- * ecc : Uncorrectable ECC error
- * bdd : dual meaing
- */
-typedef union {
- unsigned all :8;
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- unsigned mark :1;
- unsigned tzero :1;
- unsigned abrt :1;
- unsigned mcr :1;
- unsigned id :1;
- unsigned mce :1;
- unsigned ecc :1;
- unsigned bdd :1;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- unsigned bdd :1;
- unsigned ecc :1;
- unsigned mce :1;
- unsigned id :1;
- unsigned mcr :1;
- unsigned abrt :1;
- unsigned tzero :1;
- unsigned mark :1;
-#else
-#error "Please fix <asm/byteorder.h>"
-#endif
- } b;
-} ata_error_t;
-
/*
* ATA-IDE Select Register, aka Device-Head
*
} b;
} ata_status_t, atapi_status_t;
-/*
- * ATA-IDE Control Register
- *
- * bit0 : Should be set to zero
- * nIEN : device INTRQ to host
- * SRST : host soft reset bit
- * bit3 : ATA-2 thingy, Should be set to 1
- * reserved456 : Reserved
- * HOB : 48-bit address ordering, High Ordered Bit
- */
-typedef union {
- unsigned all : 8;
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- unsigned bit0 : 1;
- unsigned nIEN : 1;
- unsigned SRST : 1;
- unsigned bit3 : 1;
- unsigned reserved456 : 3;
- unsigned HOB : 1;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- unsigned HOB : 1;
- unsigned reserved456 : 3;
- unsigned bit3 : 1;
- unsigned SRST : 1;
- unsigned nIEN : 1;
- unsigned bit0 : 1;
-#else
-#error "Please fix <asm/byteorder.h>"
-#endif
- } b;
-} ata_control_t;
-
/*
* ATAPI Feature Register
*
} b;
} atapi_error_t;
-/*
- * ATAPI floppy Drive Select Register
- *
- * sam_lun : Logical unit number
- * reserved3 : Reserved
- * drv : The responding drive will be drive 0 (0) or drive 1 (1)
- * one5 : Should be set to 1
- * reserved6 : Reserved
- * one7 : Should be set to 1
- */
-typedef union {
- unsigned all :8;
- struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
- unsigned sam_lun :3;
- unsigned reserved3 :1;
- unsigned drv :1;
- unsigned one5 :1;
- unsigned reserved6 :1;
- unsigned one7 :1;
-#elif defined(__BIG_ENDIAN_BITFIELD)
- unsigned one7 :1;
- unsigned reserved6 :1;
- unsigned one5 :1;
- unsigned drv :1;
- unsigned reserved3 :1;
- unsigned sam_lun :3;
-#else
-#error "Please fix <asm/byteorder.h>"
-#endif
- } b;
-} atapi_select_t;
-
/*
* Status returned from various ide_ functions
*/
int (*end_request)(ide_drive_t *, int, int);
ide_startstop_t (*error)(ide_drive_t *, struct request *rq, u8, u8);
ide_startstop_t (*abort)(ide_drive_t *, struct request *rq);
- int (*ioctl)(ide_drive_t *, struct inode *, struct file *, unsigned int, unsigned long);
ide_proc_entry_t *proc;
- void (*ata_prebuilder)(ide_drive_t *);
- void (*atapi_prebuilder)(ide_drive_t *);
struct device_driver gen_driver;
} ide_driver_t;
extern void ide_timer_expiry(unsigned long);
extern irqreturn_t ide_intr(int irq, void *dev_id, struct pt_regs *regs);
extern void do_ide_request(request_queue_t *);
-extern void ide_init_subdrivers(void);
void ide_init_disk(struct gendisk *, ide_drive_t *);
#define GOOD_DMA_DRIVE 1
#ifdef CONFIG_BLK_DEV_IDEDMA
+struct drive_list_entry {
+ const char *id_model;
+ const char *id_firmware;
+};
+
+int ide_in_drive_list(struct hd_driveid *, const struct drive_list_entry *);
int __ide_dma_bad_drive(ide_drive_t *);
int __ide_dma_good_drive(ide_drive_t *);
int ide_use_dma(ide_drive_t *);
ATA_FLAG_NOINTR = (1 << 9), /* FIXME: Remove this once
* proper HSM is in place. */
ATA_FLAG_DEBUGMSG = (1 << 10),
+ ATA_FLAG_NO_ATAPI = (1 << 11), /* No ATAPI support */
ATA_QCFLAG_ACTIVE = (1 << 1), /* cmd not yet ack'd to scsi lyer */
ATA_QCFLAG_SG = (1 << 3), /* have s/g table? */
#define VM_HUGETLB 0x00400000 /* Huge TLB Page VM */
#define VM_NONLINEAR 0x00800000 /* Is non-linear (remap_file_pages) */
#define VM_MAPPED_COPY 0x01000000 /* T if mapped copy of data (nommu mmap) */
+#define VM_INSERTPAGE 0x02000000 /* The vma has had "vm_insert_page()" done on it */
#ifndef VM_STACK_DEFAULT_FLAGS /* arch can override this */
#define VM_STACK_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS
#define PCI_DEVICE_ID_VIA_8378_0 0x3205
#define PCI_DEVICE_ID_VIA_8783_0 0x3208
#define PCI_DEVICE_ID_VIA_8237 0x3227
+#define PCI_DEVICE_ID_VIA_8251 0x3287
#define PCI_DEVICE_ID_VIA_3296_0 0x0296
#define PCI_DEVICE_ID_VIA_8231 0x8231
#define PCI_DEVICE_ID_VIA_8231_4 0x8235
extern void scsi_put_command(struct scsi_cmnd *);
extern void scsi_io_completion(struct scsi_cmnd *, unsigned int, unsigned int);
extern void scsi_finish_command(struct scsi_cmnd *cmd);
+extern void scsi_setup_blk_pc_cmnd(struct scsi_cmnd *cmd, int retries);
#endif /* _SCSI_SCSI_CMND_H */
outside the kernel tree does. Such modules require Y here.
config KOBJECT_UEVENT
- bool "Kernel Userspace Events"
+ bool "Kernel Userspace Events" if EMBEDDED
depends on NET
default y
help
source "usr/Kconfig"
+config CC_OPTIMIZE_FOR_SIZE
+ bool "Optimize for size (Look out for broken compilers!)"
+ default y
+ depends on ARM || H8300 || EXPERIMENTAL
+ depends on !SPARC64
+ help
+ Enabling this option will pass "-Os" instead of "-O2" to gcc
+ resulting in a smaller kernel.
+
+ WARNING: some versions of gcc may generate incorrect code with this
+ option. If problems are observed, a gcc upgrade may be needed.
+
+ If unsure, say N.
+
menuconfig EMBEDDED
bool "Configure standard kernel features (for small systems)"
help
Disabling this option will cause the kernel to be built without
support for epoll family of system calls.
-config CC_OPTIMIZE_FOR_SIZE
- bool "Optimize for size" if EMBEDDED
- default y if ARM || H8300
- help
- Enabling this option will pass "-Os" instead of "-O2" to gcc
- resulting in a smaller kernel.
-
- WARNING: some versions of gcc may generate incorrect code with this
- option. If problems are observed, a gcc upgrade may be needed.
-
- If unsure, say N.
-
config SHMEM
bool "Use full shmem filesystem" if EMBEDDED
default y
* readonly mappings. The tradeoff is that copy_page_range is more
* efficient than faulting.
*/
- if (!(vma->vm_flags & (VM_HUGETLB|VM_NONLINEAR|VM_PFNMAP))) {
+ if (!(vma->vm_flags & (VM_HUGETLB|VM_NONLINEAR|VM_PFNMAP|VM_INSERTPAGE))) {
if (!vma->anon_vma)
return 0;
}
return -EFAULT;
if (!page_count(page))
return -EINVAL;
+ vma->vm_flags |= VM_INSERTPAGE;
return insert_page(vma->vm_mm, addr, page, vma->vm_page_prot);
}
EXPORT_SYMBOL(vm_insert_page);
pgdat->node_start_pfn = start_pfn;
if (end_pfn > old_pgdat_end_pfn)
- pgdat->node_spanned_pages = end_pfn - pgdat->node_spanned_pages;
+ pgdat->node_spanned_pages = end_pfn - pgdat->node_start_pfn;
}
int online_pages(unsigned long pfn, unsigned long nr_pages)
* If the vma has a ->close operation then the driver probably needs to release
* per-vma resources, so we don't attempt to merge those.
*/
-#define VM_SPECIAL (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_RESERVED)
+#define VM_SPECIAL (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_RESERVED | VM_PFNMAP)
static inline int is_mergeable_vma(struct vm_area_struct *vma,
struct file *file, unsigned long vm_flags)
/* We can't remap across vm area boundaries */
if (old_len > vma->vm_end - addr)
goto out;
- if (vma->vm_flags & VM_DONTEXPAND) {
+ if (vma->vm_flags & (VM_DONTEXPAND | VM_PFNMAP)) {
if (new_len > old_len)
goto out;
}
static struct notifier_block pageset_notifier =
{ &pageset_cpuup_callback, NULL, 0 };
-void __init setup_per_cpu_pageset()
+void __init setup_per_cpu_pageset(void)
{
int err;
skb_pull(skb, VLAN_HLEN); /* take off the VLAN header (4 bytes currently) */
+ /* Need to correct hardware checksum */
+ skb_postpull_rcsum(skb, vhdr, VLAN_HLEN);
+
/* Ok, lets check to make sure the device (dev) we
* came in on is what this VLAN is attached to.
*/
config IEEE80211_CRYPT_TKIP
tristate "IEEE 802.11i TKIP encryption"
- depends on IEEE80211
+ depends on IEEE80211 && NET_RADIO
select CRYPTO
select CRYPTO_MICHAEL_MIC
---help---
skb->mac.raw = skb->nh.raw;
skb->nh.raw = __pskb_pull(skb, offset);
- skb_postpull_rcsum(skb, skb->mac.raw, offset);
+ skb_postpull_rcsum(skb, skb->h.raw, offset);
memset(&(IPCB(skb)->opt), 0, sizeof(struct ip_options));
skb->pkt_type = PACKET_HOST;
#ifdef CONFIG_NET_IPGRE_BROADCAST
dev->type == ARPHRD_NONE ||
dev->type == ARPHRD_SIT) {
printk(KERN_INFO
- "Disabled Privacy Extensions on device %p(%s)\n",
- dev, dev->name);
+ "%s: Disabled Privacy Extensions\n",
+ dev->name);
ndev->cnf.use_tempaddr = -1;
} else {
in6_dev_hold(ndev);
#include <net/sch_generic.h>
#include <net/act_api.h>
-#if 1 /* control */
+#if 0 /* control */
#define DPRINTK(format, args...) printk(KERN_DEBUG format, ##args)
#else
#define DPRINTK(format, args...)
}
static int sctp_copy_laddrs_to_user(struct sock *sk, __u16 port,
- void * __user *to, size_t space_left)
+ void __user **to, size_t space_left)
{
struct list_head *pos;
struct sctp_sockaddr_entry *addr;
} while ((stat & PSC_AC97STAT_DR) == 0);
}
+/* Hold spinlock for both start_dac() and start_adc() calls */
static void
start_dac(struct au1550_state *s)
{
struct dmabuf *db = &s->dma_dac;
- unsigned long flags;
if (!db->stopped)
return;
- spin_lock_irqsave(&s->lock, flags);
-
set_xmit_slots(db->num_channels);
au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
au_sync();
au1xxx_dbdma_start(db->dmanr);
db->stopped = 0;
-
- spin_unlock_irqrestore(&s->lock, flags);
}
static void
}
-/* hold spinlock for the following */
static void
dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct dmabuf *db = &s->dma_dac;
u32 ac97c_stat;
+ spin_lock(&s->lock);
+
ac97c_stat = au_readl(PSC_AC97STAT);
if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
/* wake up anybody listening */
if (waitqueue_active(&db->wait))
wake_up(&db->wait);
+
+ spin_unlock(&s->lock);
}
u32 obytes;
char *obuf;
+ spin_lock(&s->lock);
+
/* Pull the buffer from the dma queue.
*/
au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
if ((dp->count + obytes) > dp->dmasize) {
/* Overrun. Stop ADC and log the error
*/
+ spin_unlock(&s->lock);
stop_adc(s);
dp->error++;
err("adc overrun");
if (waitqueue_active(&dp->wait))
wake_up(&dp->wait);
+ spin_unlock(&s->lock);
}
static loff_t
/* wait for samples in ADC dma buffer
*/
do {
+ spin_lock_irqsave(&s->lock, flags);
if (db->stopped)
start_adc(s);
- spin_lock_irqsave(&s->lock, flags);
avail = db->count;
if (avail <= 0)
__set_current_state(TASK_INTERRUPTIBLE);
if (get_user(val, (int *) arg))
return -EFAULT;
if (file->f_mode & FMODE_READ) {
- if (val & PCM_ENABLE_INPUT)
+ if (val & PCM_ENABLE_INPUT) {
+ spin_lock_irqsave(&s->lock, flags);
start_adc(s);
- else
+ spin_unlock_irqrestore(&s->lock, flags);
+ } else
stop_adc(s);
}
if (file->f_mode & FMODE_WRITE) {
- if (val & PCM_ENABLE_OUTPUT)
+ if (val & PCM_ENABLE_OUTPUT) {
+ spin_lock_irqsave(&s->lock, flags);
start_dac(s);
- else
+ spin_unlock_irqrestore(&s->lock, flags);
+ } else
stop_dac(s);
}
return 0;
projects / linux-2.6-omap-h63xx.git / commitdiff