#define OMAP3430ES2_ST_USBTLL_MASK                     (1 << 2)
 
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430ES2_AUTO_MMC3                          (1 << 30)
+#define OMAP3430ES2_AUTO_MMC3_SHIFT                    30
+#define OMAP3430ES2_AUTO_ICR                           (1 << 29)
+#define OMAP3430ES2_AUTO_ICR_SHIFT                     29
 #define OMAP3430_AUTO_AES2                             (1 << 28)
 #define OMAP3430_AUTO_AES2_SHIFT                       28
 #define OMAP3430_AUTO_SHA12                            (1 << 27)
 #define OMAP3430_AUTO_DES1_SHIFT                       0
 
 /* CM_AUTOIDLE3_CORE */
+#define        OMAP3430ES2_AUTO_USBHOST                        (1 << 0)
+#define        OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define        OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                  2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                   (1 << 2)
 
 
 
 /* PM_WKEN_WKUP specific bits */
 #define OMAP3430_EN_IO                                 (1 << 8)
+#define OMAP3430_EN_GPIO1                              (1 << 3)
 
 /* PM_MPUGRPSEL_WKUP specific bits */
 
 #define OMAP3430_CMDRA0_MASK                           (0xff << 0)
 
 /* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_ON_SHIFT                       24
+#define OMAP3430_VC_CMD_ON_MASK                                (0xFF << 24)
+#define OMAP3430_VC_CMD_ONLP_SHIFT                     16
+#define OMAP3430_VC_CMD_ONLP_MASK                      (0xFF << 16)
+#define OMAP3430_VC_CMD_RET_SHIFT                      8
+#define OMAP3430_VC_CMD_RET_MASK                       (0xFF << 8)
+#define OMAP3430_VC_CMD_OFF_SHIFT                      0
+#define OMAP3430_VC_CMD_OFF_MASK                       (0xFF << 0)
 
 /* PRM_VC_CMD_VAL_1 specific bits */
 
 
 #define PM_PWSTCTRL                                    0x00e0
 #define PM_PWSTST                                      0x00e4
 
+/* Omap2 specific registers */
+#define OMAP24XX_PM_WKEN2                              0x00a4
+#define OMAP24XX_PM_WKST2                              0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                    0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                    0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                    0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                    0x00fc
+
+/* Omap3 specific registers */
+#define OMAP3430ES2_PM_WKEN3                           0x00f0
+#define OMAP3430ES2_PM_WKST3                           0x00b8
+
 #define OMAP3430_PM_MPUGRPSEL                          0x00a4
 #define OMAP3430_PM_MPUGRPSEL1                         OMAP3430_PM_MPUGRPSEL
 
        return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
 
-/* Architecture-specific registers */
-
-#define OMAP24XX_PM_WKEN2                              0x00a4
-#define OMAP24XX_PM_WKST2                              0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                    0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                    0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                    0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                    0x00fc
-
 /* Power/reset management domain register get/set */
 
 static __inline__ void __attribute__((unused)) prm_write_mod_reg(u32 val,
 #define OMAP_RSTTIME1_SHIFT                            0
 #define OMAP_RSTTIME1_MASK                             (0xff << 0)
 
-
 /* PRM_RSTCTRL */
 /* Named RM_RSTCTRL_WKUP on the 24xx */
 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 
 #define INT_34XX_ST_MCBSP2_IRQ 4
 #define INT_34XX_ST_MCBSP3_IRQ 5
 #define INT_34XX_SYS_NIRQ      7
+#define INT_34XX_PRCM_MPU_IRQ  11
 #define INT_34XX_MCBSP1_IRQ    16
 #define INT_34XX_MCBSP2_IRQ    17
 #define INT_34XX_MCBSP3_IRQ    22