x86: Centaur Isaiah processor to use sysenter in 64-bit compatibility mode rather...

Upcoming 64 bit processors from Centaur can use sysenter.

Signed-off-by: Dave Jones <davej@codemonkey.org.uk>
Signed-off-by: Jesse Ahrens <jahrens@centtech.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 540686be35d0d917e6a86901b6ed4ca7e48f8f2a..b80300710c081bc46442f92cd6830f433e9ff0b2 100644 (file)
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -885,6 +885,32 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
        srat_detect_node();
 }
 
+static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
+{
+       if (c->x86 == 0x6 && c->x86_model >= 0xf)
+               set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
+}
+
+static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
+{
+       /* Cache sizes */
+       unsigned n;
+
+       n = c->extended_cpuid_level;
+       if (n >= 0x80000008) {
+               unsigned eax = cpuid_eax(0x80000008);
+               c->x86_virt_bits = (eax >> 8) & 0xff;
+               c->x86_phys_bits = eax & 0xff;
+       }
+
+       if (c->x86 == 0x6 && c->x86_model >= 0xf) {
+               c->x86_cache_alignment = c->x86_clflush_size * 2;
+               set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+               set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+       }
+       set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+}
+
 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 {
        char *v = c->x86_vendor_id;
@@ -893,6 +919,8 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
                c->x86_vendor = X86_VENDOR_AMD;
        else if (!strcmp(v, "GenuineIntel"))
                c->x86_vendor = X86_VENDOR_INTEL;
+       else if (!strcmp(v, "CentaurHauls"))
+               c->x86_vendor = X86_VENDOR_CENTAUR;
        else
                c->x86_vendor = X86_VENDOR_UNKNOWN;
 }
@@ -989,6 +1017,9 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
                if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
                        set_cpu_cap(c, X86_FEATURE_PAT);
                break;
+       case X86_VENDOR_CENTAUR:
+               early_init_centaur(c);
+               break;
        }
 
 }
@@ -1025,6 +1056,10 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                init_intel(c);
                break;
 
+       case X86_VENDOR_CENTAUR:
+               init_centaur(c);
+               break;
+
        case X86_VENDOR_UNKNOWN:
        default:
                display_cacheinfo(c);

diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index f7e78d84fc0183b6345d11fb38af0a70bb070201..e2af8eee80e35b2915c461b469be6c0a4eb0f804 100644 (file)
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -210,8 +210,12 @@ static int use_sysenter __read_mostly = -1;
 /* May not be __init: called during resume */
 void syscall32_cpu_init(void)
 {
-       if (use_sysenter < 0)
-               use_sysenter = (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL);
+       if (use_sysenter < 0) {
+               if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+                       use_sysenter = 1;
+               if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR)
+                       use_sysenter = 1;
+       }
 
        /* Load these always in case some future AMD CPU supports
           SYSENTER from compat mode too. */