ARM: OMAP: SoSSI: fix write / read cycle to tw1 mapping

A read / write cycle is defined by tw0 + tw1. It was wrongly assumed that
the 1 cycle long CS active edge to read / write active edge is part of
each cycle, thus we ended up with too low tw1 value -> too short cycle
time.

Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>

diff --git a/drivers/video/omap/sossi.c b/drivers/video/omap/sossi.c
index 6e8142ba5f7bf4a32285a1227a807629f0051602..64dd0a46e5155a7cbf9ccbf64c03c3f2802350e6 100644 (file)
--- a/drivers/video/omap/sossi.c
+++ b/drivers/video/omap/sossi.c
@@ -239,7 +239,7 @@ static int calc_rd_timings(struct extif_timings *t)
        if (recyc <= reoff)
                recyc = reoff + 1;
 
-       tw1 = recyc - reoff;
+       tw1 = recyc - tw0;
        /* values less then 3 result in the SOSSI block resetting itself */
        if (tw1 < 3)
                tw1 = 3;
@@ -286,7 +286,7 @@ static int calc_wr_timings(struct extif_timings *t)
        if (wecyc <= weoff)
                wecyc = weoff + 1;
 
-       tw1 = wecyc - weoff;
+       tw1 = wecyc - tw0;
        /* values less then 3 result in the SOSSI block resetting itself */
        if (tw1 < 3)
                tw1 = 3;