}
 }
 
+static void nv_napi_enable(struct net_device *dev)
+{
+#ifdef CONFIG_FORCEDETH_NAPI
+       struct fe_priv *np = get_nvpriv(dev);
+
+       napi_enable(&np->napi);
+#endif
+}
+
+static void nv_napi_disable(struct net_device *dev)
+{
+#ifdef CONFIG_FORCEDETH_NAPI
+       struct fe_priv *np = get_nvpriv(dev);
+
+       napi_disable(&np->napi);
+#endif
+}
+
 #define MII_READ       (-1)
 /* mii_rw: read/write a register on the PHY.
  *
                 * Changing the MTU is a rare event, it shouldn't matter.
                 */
                nv_disable_irq(dev);
+               nv_napi_disable(dev);
                netif_tx_lock_bh(dev);
                netif_addr_lock(dev);
                spin_lock(&np->lock);
                spin_unlock(&np->lock);
                netif_addr_unlock(dev);
                netif_tx_unlock_bh(dev);
+               nv_napi_enable(dev);
                nv_enable_irq(dev);
        }
        return 0;
 
        if (netif_running(dev)) {
                nv_disable_irq(dev);
+               nv_napi_disable(dev);
                netif_tx_lock_bh(dev);
                netif_addr_lock(dev);
                spin_lock(&np->lock);
                spin_unlock(&np->lock);
                netif_addr_unlock(dev);
                netif_tx_unlock_bh(dev);
+               nv_napi_enable(dev);
                nv_enable_irq(dev);
        }
        return 0;
        if (test->flags & ETH_TEST_FL_OFFLINE) {
                if (netif_running(dev)) {
                        netif_stop_queue(dev);
-#ifdef CONFIG_FORCEDETH_NAPI
-                       napi_disable(&np->napi);
-#endif
+                       nv_napi_disable(dev);
                        netif_tx_lock_bh(dev);
                        netif_addr_lock(dev);
                        spin_lock_irq(&np->lock);
                        /* restart rx engine */
                        nv_start_rxtx(dev);
                        netif_start_queue(dev);
-#ifdef CONFIG_FORCEDETH_NAPI
-                       napi_enable(&np->napi);
-#endif
+                       nv_napi_enable(dev);
                        nv_enable_hw_interrupts(dev, np->irqmask);
                }
        }
        ret = nv_update_linkspeed(dev);
        nv_start_rxtx(dev);
        netif_start_queue(dev);
-#ifdef CONFIG_FORCEDETH_NAPI
-       napi_enable(&np->napi);
-#endif
+       nv_napi_enable(dev);
 
        if (ret) {
                netif_carrier_on(dev);
        spin_lock_irq(&np->lock);
        np->in_shutdown = 1;
        spin_unlock_irq(&np->lock);
-#ifdef CONFIG_FORCEDETH_NAPI
-       napi_disable(&np->napi);
-#endif
+       nv_napi_disable(dev);
        synchronize_irq(np->pci_dev->irq);
 
        del_timer_sync(&np->oom_kick);