- /*
- * Mark the device areas according to the CPU/architecture.
- */
- if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
- if (!cpu_is_xsc3()) {
- /*
- * Mark device regions on ARMv6+ as execute-never
- * to prevent speculative instruction fetches.
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
- }
- if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
- /*
- * For ARMv7 with TEX remapping,
- * - shared device is SXCB=1100
- * - nonshared device is SXCB=0100
- * - write combine device mem is SXCB=0001
- * (Uncached Normal memory)
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
- } else {
- /*
- * For Xscale3, ARMv6 and ARMv7 without TEX remapping,
- * - shared device is TEXCB=00001
- * - nonshared device is TEXCB=01000
- * - write combine device mem is TEXCB=00100
- * (Inner/Outer Uncacheable in xsc3 parlance, Uncached
- * Normal in ARMv6 parlance).
- */
- mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
- mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
- }
- } else {
- /*
- * On others, write combining is "Uncached/Buffered"
- */
- mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
- }
-
- /*
- * Now deal with the memory-type mappings
- */