-#define CFC_COMMON_END 1055
-#define HC_COMMON_START 1055
- {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
-#define HC_COMMON_END 1056
-#define HC_PORT0_START 1056
- {OP_WR, HC_REG_CONFIG_0, 0x1080},
- {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2},
- {OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
- {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff},
- {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff},
- {OP_WR, HC_REG_AGG_INT_0, 0x0},
- {OP_WR, HC_REG_ATTN_IDX, 0x0},
- {OP_ZR, HC_REG_ATTN_BIT, 0x2},
- {OP_WR, HC_REG_VQID_0, 0x2b5},
- {OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
- {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
- {OP_ZR, HC_REG_PBA_COMMAND, 0x2},
- {OP_WR, HC_REG_INT_MASK, 0x1ffff},
- {OP_WR, HC_REG_CONFIG_0, 0x1a82},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_PORT0_END 1074
-#define HC_PORT1_START 1074
- {OP_WR, HC_REG_CONFIG_1, 0x1080},
- {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2},
- {OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
- {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff},
- {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff},
- {OP_WR, HC_REG_AGG_INT_1, 0x0},
- {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
- {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
- {OP_WR, HC_REG_VQID_1, 0x2b5},
- {OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
- {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
- {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
- {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
- {OP_WR, HC_REG_CONFIG_1, 0x1a82},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
- {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_PORT1_END 1092
-#define PXP2_COMMON_START 1092
- {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38324},
+#define CFC_COMMON_END 1786
+#define HC_COMMON_START 1786
+ {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
+#define HC_COMMON_END 1787
+#define HC_PORT0_START 1787
+ {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
+ {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
+ {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
+ {OP_WR_E1, HC_REG_LEADING_EDGE_0, 0xffff},
+ {OP_WR_E1, HC_REG_TRAILING_EDGE_0, 0xffff},
+ {OP_WR_E1, HC_REG_AGG_INT_0, 0x0},
+ {OP_WR_E1, HC_REG_ATTN_IDX, 0x0},
+ {OP_ZR_E1, HC_REG_ATTN_BIT, 0x2},
+ {OP_WR_E1, HC_REG_VQID_0, 0x2b5},
+ {OP_WR_E1, HC_REG_PCI_CONFIG_0, 0x0},
+ {OP_ZR_E1, HC_REG_P0_PROD_CONS, 0x4a},
+ {OP_WR_E1, HC_REG_INT_MASK, 0x1ffff},
+ {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
+ {OP_WR_E1, HC_REG_CONFIG_0, 0x1a80},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS, 0x24},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+ {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
+#define HC_PORT0_END 1806
+#define HC_PORT1_START 1806
+ {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
+ {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
+ {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
+ {OP_WR_E1, HC_REG_LEADING_EDGE_1, 0xffff},
+ {OP_WR_E1, HC_REG_TRAILING_EDGE_1, 0xffff},
+ {OP_WR_E1, HC_REG_AGG_INT_1, 0x0},
+ {OP_WR_E1, HC_REG_ATTN_IDX + 0x4, 0x0},
+ {OP_ZR_E1, HC_REG_ATTN_BIT + 0x8, 0x2},
+ {OP_WR_E1, HC_REG_VQID_1, 0x2b5},
+ {OP_WR_E1, HC_REG_PCI_CONFIG_1, 0x0},
+ {OP_ZR_E1, HC_REG_P1_PROD_CONS, 0x4a},
+ {OP_WR_E1, HC_REG_INT_MASK + 0x4, 0x1ffff},
+ {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
+ {OP_WR_E1, HC_REG_CONFIG_1, 0x1a80},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+ {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+ {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
+#define HC_PORT1_END 1825
+#define HC_FUNC0_START 1825
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
+ {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+#define HC_FUNC0_END 1840
+#define HC_FUNC1_START 1840
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
+ {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+#define HC_FUNC1_END 1855
+#define HC_FUNC2_START 1855
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
+ {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+#define HC_FUNC2_END 1870
+#define HC_FUNC3_START 1870
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
+ {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+#define HC_FUNC3_END 1885
+#define HC_FUNC4_START 1885
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
+ {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+#define HC_FUNC4_END 1900
+#define HC_FUNC5_START 1900
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
+ {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+#define HC_FUNC5_END 1915
+#define HC_FUNC6_START 1915
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
+ {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
+#define HC_FUNC6_END 1930
+#define HC_FUNC7_START 1930
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
+ {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
+ {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
+ {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
+ {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
+ {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
+ {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
+ {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
+ {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
+ {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
+ {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
+#define HC_FUNC7_END 1945
+#define PXP2_COMMON_START 1945
+ {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
+ {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},