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e9ea612)
When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use
the user's desired rate in clk->rate to determine whether to put the
DPLL into bypass or lock mode, rather than reading the DPLL's current
idle state from its hardware registers.
This fixes a bug observed when leaving retention. Non-CORE DPLLs were
not being relocked when downstream clocks re-enabled; rather, the DPLL
entered bypass mode.
Problem reported by Tero Kristo <tero.kristo@nokia.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- rate = omap2_get_dpll_rate(clk);
-
- if (dd->bypass_clk->rate == rate)
+ if (clk->rate == dd->bypass_clk->rate)
r = _omap3_noncore_dpll_bypass(clk);
else
r = _omap3_noncore_dpll_lock(clk);
r = _omap3_noncore_dpll_bypass(clk);
else
r = _omap3_noncore_dpll_lock(clk);