Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404). This patch gets the structs back in sync
with the spec.
Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
* error occurred
*/
wiv : 1, /* Way field valid */
* error occurred
*/
wiv : 1, /* Way field valid */
+ reserved2 : 1,
+ dp : 1, /* Data poisoned on MBE */
+ reserved3 : 8,
index : 20, /* Cache line index */
index : 20, /* Cache line index */
is : 1, /* instruction set (1 == ia32) */
iv : 1, /* instruction set field valid */
is : 1, /* instruction set (1 == ia32) */
iv : 1, /* instruction set field valid */
type : 8, /* Bus xaction type*/
sev : 5, /* Bus error severity*/
hier : 2, /* Bus hierarchy level */
type : 8, /* Bus xaction type*/
sev : 5, /* Bus error severity*/
hier : 2, /* Bus hierarchy level */
+ dp : 1, /* Data poisoned on MBE */
bsi : 8, /* Bus error status
* info
*/
bsi : 8, /* Bus error status
* info
*/