Update the S3C2443 clock support to add the prediv clock
that is sourced via a divider from msysclk. Also fix the
setting of p and h clocks from this prediv clock.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
.round_rate = s3c2443_roundrate_clksrc256,
};
.round_rate = s3c2443_roundrate_clksrc256,
};
+/* prediv
+ *
+ * this divides the msysclk down to pass to h/p/etc.
+ */
+
+static unsigned long s3c2443_prediv_getrate(struct clk *clk)
+{
+ unsigned long rate = clk_get_rate(clk->parent);
+ unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+ clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+ clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+ return rate / (clkdiv0 + 1);
+}
+
+static struct clk clk_prediv = {
+ .name = "prediv",
+ .id = -1,
+ .parent = &clk_msysclk,
+ .get_rate = s3c2443_prediv_getrate,
+};
+
/* standard clock definitions */
static struct clk init_clocks_disable[] = {
/* standard clock definitions */
static struct clk init_clocks_disable[] = {
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
}
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
}
-static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
+static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
- clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
- clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+ clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
&clk_hsmmc,
&clk_armdiv,
&clk_arm,
&clk_hsmmc,
&clk_armdiv,
&clk_arm,
};
void __init s3c2443_init_clocks(int xtal)
};
void __init s3c2443_init_clocks(int xtal)
+ /* s3c2443 parents h and p clocks from prediv */
+ clk_h.parent = &clk_prediv;
+ clk_p.parent = &clk_prediv;
+
pll = s3c2443_get_mpll(mpllcon, xtal);
pll = s3c2443_get_mpll(mpllcon, xtal);
+ clk_msysclk.rate = pll;
fclk = pll / s3c2443_fclk_div(clkdiv0);
fclk = pll / s3c2443_fclk_div(clkdiv0);
- hclk = fclk / s3c2443_get_prediv(clkdiv0);
+ hclk = s3c2443_prediv_getrate(&clk_prediv);
+ hclk = hclk / s3c2443_get_hdiv(clkdiv0);
hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
- clk_armdiv.rate = fclk;
-
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",