Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This driver supports the Gigabit Ethernet mode of the QUICC Engine,
which is available on some Freescale SOCs.
This driver supports the Gigabit Ethernet mode of the QUICC Engine,
which is available on some Freescale SOCs.
-config UGETH_NAPI
- bool "Use Rx Polling (NAPI)"
- depends on UCC_GETH
-
config UGETH_MAGIC_PACKET
bool "Magic Packet detection support"
depends on UCC_GETH
config UGETH_MAGIC_PACKET
bool "Magic Packet detection support"
depends on UCC_GETH
dev->stats.rx_bytes += length;
/* Send the packet up the stack */
dev->stats.rx_bytes += length;
/* Send the packet up the stack */
-#ifdef CONFIG_UGETH_NAPI
-#else
- netif_rx(skb);
-#endif /* CONFIG_UGETH_NAPI */
}
ugeth->dev->last_rx = jiffies;
}
ugeth->dev->last_rx = jiffies;
-#ifdef CONFIG_UGETH_NAPI
static int ucc_geth_poll(struct napi_struct *napi, int budget)
{
struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
static int ucc_geth_poll(struct napi_struct *napi, int budget)
{
struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
-#endif /* CONFIG_UGETH_NAPI */
static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
{
static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
{
struct ucc_geth_info *ug_info;
register u32 ucce;
register u32 uccm;
struct ucc_geth_info *ug_info;
register u32 ucce;
register u32 uccm;
-#ifndef CONFIG_UGETH_NAPI
- register u32 rx_mask;
-#endif
register u32 tx_mask;
u8 i;
register u32 tx_mask;
u8 i;
/* check for receive events that require processing */
if (ucce & UCCE_RX_EVENTS) {
/* check for receive events that require processing */
if (ucce & UCCE_RX_EVENTS) {
-#ifdef CONFIG_UGETH_NAPI
if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
uccm &= ~UCCE_RX_EVENTS;
out_be32(uccf->p_uccm, uccm);
__netif_rx_schedule(dev, &ugeth->napi);
}
if (netif_rx_schedule_prep(dev, &ugeth->napi)) {
uccm &= ~UCCE_RX_EVENTS;
out_be32(uccf->p_uccm, uccm);
__netif_rx_schedule(dev, &ugeth->napi);
}
-#else
- rx_mask = UCCE_RXBF_SINGLE_MASK;
- for (i = 0; i < ug_info->numQueuesRx; i++) {
- if (ucce & rx_mask)
- ucc_geth_rx(ugeth, i, (int)ugeth->ug_info->bdRingLenRx[i]);
- ucce &= ~rx_mask;
- rx_mask <<= 1;
- }
-#endif /* CONFIG_UGETH_NAPI */
}
/* Tx event processing */
}
/* Tx event processing */
-#ifdef CONFIG_UGETH_NAPI
napi_enable(&ugeth->napi);
napi_enable(&ugeth->napi);
err = ucc_geth_startup(ugeth);
if (err) {
if (netif_msg_ifup(ugeth))
err = ucc_geth_startup(ugeth);
if (err) {
if (netif_msg_ifup(ugeth))
-#ifdef CONFIG_UGETH_NAPI
napi_disable(&ugeth->napi);
napi_disable(&ugeth->napi);
ugeth_vdbg("%s: IN", __FUNCTION__);
ugeth_vdbg("%s: IN", __FUNCTION__);
-#ifdef CONFIG_UGETH_NAPI
napi_disable(&ugeth->napi);
napi_disable(&ugeth->napi);
dev->hard_start_xmit = ucc_geth_start_xmit;
dev->tx_timeout = ucc_geth_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
dev->hard_start_xmit = ucc_geth_start_xmit;
dev->tx_timeout = ucc_geth_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
-#ifdef CONFIG_UGETH_NAPI
netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
-#endif /* CONFIG_UGETH_NAPI */
#ifdef CONFIG_NET_POLL_CONTROLLER
dev->poll_controller = ucc_netpoll;
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
dev->poll_controller = ucc_netpoll;
#endif