Two issues are fixed here:
- I2S transmits the left frame with the clock low but I don't seem to
get LRCLK out without SFRMDLY being set so invert SFRMP and set a
delay.
- I2S has a clock cycle prior to the first data byte in each channel
so we need to delay the data by one cycle.
Tested-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
/*
* pxa-ssp.c -- ALSA Soc Audio Layer
*
/*
* pxa-ssp.c -- ALSA Soc Audio Layer
*
sscr0 |= SSCR0_PSP;
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
sscr0 |= SSCR0_PSP;
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
break;
case SND_SOC_DAIFMT_NB_IF:
break;
case SND_SOC_DAIFMT_IB_IF:
break;
case SND_SOC_DAIFMT_IB_IF:
- sspsp |= SSPSP_SFRMP | SSPSP_SCMODE(3);
+ sspsp |= SSPSP_SCMODE(3);
break;
default:
return -EINVAL;
break;
default:
return -EINVAL;
#else
return -EINVAL;
#endif
#else
return -EINVAL;
#endif
- } else
- sspsp |= SSPSP_SFRMWDTH(width);
+ } else {
+ /* The frame width is the width the LRCLK is
+ * asserted for; the delay is expressed in
+ * half cycle units. We need the extra cycle
+ * because the data starts clocking out one BCLK
+ * after LRCLK changes polarity.
+ */
+ sspsp |= SSPSP_SFRMWDTH(width + 1);
+ sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
+ sspsp |= SSPSP_DMYSTRT(1);
+ }
ssp_write_reg(ssp, SSPSP, sspsp);
break;
ssp_write_reg(ssp, SSPSP, sspsp);
break;