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[XTENSA] Fix icache flush for cache aliasing
authorChris Zankel <chris@zankel.net>
Tue, 12 Feb 2008 18:11:45 +0000 (10:11 -0800)
committerChris Zankel <chris@zankel.net>
Thu, 14 Feb 2008 01:08:18 +0000 (17:08 -0800)
commit0b2c3afdaaaa3e577300b2235df43eb8af00020b
treea19e12791a9d109f61f1edce731f50589302d04dtree | snapshot
parent70e137eb48f62e59dfa5e06d0d01f123e9464f9acommit | diff
[XTENSA] Fix icache flush for cache aliasing

Set the execution bit in the temporary TLB when we flush the
instruction cache.

Signed-off-by: Chris Zankel <chris@zankel.net>
arch/xtensa/mm/misc.S diff | blob | history
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