X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-x86%2Fprocessor.h;h=61c3d3005dc9a55ed01cf2a33b7a327ebeabbd25;hb=fe47784ba5cbb6b713c013e046859946789b45e4;hp=eb4bd8c0773033285781d157998b11708e98471f;hpb=83b8e28b14d63db928cb39e5c5ed2a548246bd71;p=linux-2.6-omap-h63xx.git

diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index eb4bd8c0773..61c3d3005dc 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -746,6 +746,29 @@ extern unsigned long		boot_option_idle_override;
 extern unsigned long		idle_halt;
 extern unsigned long		idle_nomwait;
 
+/*
+ * on systems with caches, caches must be flashed as the absolute
+ * last instruction before going into a suspended halt.  Otherwise,
+ * dirty data can linger in the cache and become stale on resume,
+ * leading to strange errors.
+ *
+ * perform a variety of operations to guarantee that the compiler
+ * will not reorder instructions.  wbinvd itself is serializing
+ * so the processor will not reorder.
+ *
+ * Systems without cache can just go into halt.
+ */
+static inline void wbinvd_halt(void)
+{
+	mb();
+	/* check for clflush to determine if wbinvd is legal */
+	if (cpu_has_clflush)
+		asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
+	else
+		while (1)
+			halt();
+}
+
 extern void enable_sep_cpu(void);
 extern int sysenter_setup(void);