X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-arm%2Fassembler.h;h=911393b2c6f000cc39bf84d73a7385883c105e5f;hb=2239aff6ab2b95af1f628eee7a809f21c41605b3;hp=fce8328208258bcd64cae06279608a8d4008f347;hpb=4c4925c1f4ccd72002957c3e73b4f117f2bcf712;p=linux-2.6-omap-h63xx.git

diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce83282082..911393b2c6f 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,6 +55,21 @@
 #define PLD(code...)
 #endif
 
+/*
+ * This can be used to enable code to cacheline align the destination
+ * pointer when bulk writing to memory.  Experiments on StrongARM and
+ * XScale didn't show this a worthwhile thing to do when the cache is not
+ * set to write-allocate (this would need further testing on XScale when WA
+ * is used).
+ *
+ * On Feroceon there is much to gain however, regardless of cache mode.
+ */
+#ifdef CONFIG_CPU_FEROCEON
+#define CALGN(code...) code
+#else
+#define CALGN(code...)
+#endif
+
 /*
  * Enable and disable interrupts
  */