X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Fblackfin%2Fmach-bf537%2Finclude%2Fmach%2Fbfin_serial_5xx.h;h=b86662fb9de76fad4cf16b0ee3a46e5d81db4d32;hb=d307d36adeaa70074773b3e5eab8d7e1beb008a4;hp=d46fc4f50cf2860a369c3670d4065eb174feeab2;hpb=6f95570e407d03c5140a220e054f9b18abdc7041;p=linux-2.6-omap-h63xx.git diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h index d46fc4f50cf..b86662fb9de 100644 --- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h @@ -53,9 +53,9 @@ #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) -#define UART_GET_CTS(x) gpio_get_value(x->cts_pin) -#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1) -#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0) +#define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin)) +#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) +#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) @@ -87,6 +87,7 @@ struct bfin_serial_port { struct uart_port port; unsigned int old_status; + int status_irq; unsigned int lsr; #ifdef CONFIG_SERIAL_BFIN_DMA int tx_done; @@ -124,6 +125,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) struct bfin_serial_res { unsigned long uart_base_addr; int uart_irq; + int uart_status_irq; #ifdef CONFIG_SERIAL_BFIN_DMA unsigned int uart_tx_dma_channel; unsigned int uart_rx_dma_channel; @@ -139,6 +141,7 @@ struct bfin_serial_res bfin_serial_resource[] = { { 0xFFC00400, IRQ_UART0_RX, + IRQ_UART0_ERROR, #ifdef CONFIG_SERIAL_BFIN_DMA CH_UART0_TX, CH_UART0_RX, @@ -153,6 +156,7 @@ struct bfin_serial_res bfin_serial_resource[] = { { 0xFFC02000, IRQ_UART1_RX, + IRQ_UART1_ERROR, #ifdef CONFIG_SERIAL_BFIN_DMA CH_UART1_TX, CH_UART1_RX,