X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fplat-omap%2Finclude%2Fmach%2Fmux.h;h=f4362b8682c7a01f134a3f53109af4d6ca9ea593;hb=2619bc327417f549f1c89d5ef9b4a4aa768f41a2;hp=614b2c1327c747b77b5c693979babc566bd66d02;hpb=b8cd9d056bbc5f2630ab1787dbf76f83bbb517c0;p=linux-2.6-omap-h63xx.git

diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 614b2c1327c..f4362b8682c 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -125,20 +125,64 @@
 	.pu_pd_val	= pull_mode,				\
 },
 
-
-#define PULL_DISABLED	0
-#define PULL_ENABLED	1
-
-#define PULL_DOWN	0
-#define PULL_UP		1
+/* 24xx/34xx mux bit defines */
+#define OMAP2_PULL_ENA		(1 << 3)
+#define OMAP2_PULL_UP		(1 << 4)
+#define OMAP2_ALTELECTRICALSEL	(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define OMAP3_INPUT_EN		(1 << 8)
+#define OMAP3_OFF_EN		(1 << 9)
+#define OMAP3_OFFOUT_EN		(1 << 10)
+#define OMAP3_OFFOUT_VAL	(1 << 11)
+#define OMAP3_OFF_PULL_EN	(1 << 12)
+#define OMAP3_OFF_PULL_UP	(1 << 13)
+#define OMAP3_WAKEUP_EN		(1 << 14)
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define	OMAP34XX_MUX_MODE0	0
+#define	OMAP34XX_MUX_MODE1	1
+#define	OMAP34XX_MUX_MODE2	2
+#define	OMAP34XX_MUX_MODE3	3
+#define	OMAP34XX_MUX_MODE4	4
+#define	OMAP34XX_MUX_MODE5	5
+#define	OMAP34XX_MUX_MODE6	6
+#define	OMAP34XX_MUX_MODE7	7
+
+/* 34xx active pin states */
+#define OMAP34XX_PIN_OUTPUT		0
+#define OMAP34XX_PIN_INPUT		OMAP3_INPUT_EN
+#define OMAP34XX_PIN_INPUT_PULLUP	(OMAP2_PULL_ENA | OMAP3_INPUT_EN \
+						| OMAP2_PULL_UP)
+#define OMAP34XX_PIN_INPUT_PULLDOWN	(OMAP2_PULL_ENA | OMAP3_INPUT_EN)
+
+/* 34xx off mode states */
+#define OMAP34XX_PIN_OFF_NONE           0
+#define OMAP34XX_PIN_OFF_OUTPUT_HIGH	(OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
+						| OMAP3_OFFOUT_VAL)
+#define OMAP34XX_PIN_OFF_OUTPUT_LOW	(OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
+#define OMAP34XX_PIN_OFF_INPUT_PULLUP	(OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
+						| OMAP3_OFF_PULL_UP)
+#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN	(OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
+#define OMAP34XX_PIN_OFF_WAKEUPENABLE	OMAP3_WAKEUP_EN
+
+#define MUX_CFG_34XX(desc, reg_offset, mux_value) {		\
+	.name		= desc,					\
+	.debug		= 0,					\
+	.mux_reg	= reg_offset,				\
+	.mux_val	= mux_value				\
+},
 
 struct pin_config {
-	char *name;
-	unsigned char busy;
-	unsigned char debug;
+	char 			*name;
+	const unsigned int 	mux_reg;
+	unsigned char		debug;
 
-	const char *mux_reg_name;
-	const unsigned int mux_reg;
+#if	defined(CONFIG_ARCH_OMAP34XX)
+	u16			mux_val; /* Wake-up, off mode, pull, mux mode */
+#endif
+
+#if	defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
 	const unsigned char mask_offset;
 	const unsigned char mask;
 
@@ -150,6 +194,12 @@ struct pin_config {
 	const char *pu_pd_name;
 	const unsigned int pu_pd_reg;
 	const unsigned char pu_pd_val;
+#endif
+
+#if	defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+	const char *mux_reg_name;
+#endif
+
 };
 
 enum omap730_index {
@@ -582,6 +632,15 @@ enum omap24xx_index {
 	AC7_2430_USB0HS_DATA7,
 
 	/* 2430 McBSP */
+	AD6_2430_MCBSP_CLKS,
+
+	AB2_2430_MCBSP1_CLKR,
+	AD5_2430_MCBSP1_FSR,
+	AA1_2430_MCBSP1_DX,
+	AF3_2430_MCBSP1_DR,
+	AB3_2430_MCBSP1_FSX,
+	Y9_2430_MCBSP1_CLKX,
+
 	AC10_2430_MCBSP2_FSX,
 	AD16_2430_MCBSP2_CLX,
 	AE13_2430_MCBSP2_DX,
@@ -591,6 +650,146 @@ enum omap24xx_index {
 	AE13_2430_MCBSP2_DX_OFF,
 	AD13_2430_MCBSP2_DR_OFF,
 
+	AC9_2430_MCBSP3_CLKX,
+	AE4_2430_MCBSP3_FSX,
+	AE2_2430_MCBSP3_DR,
+	AF4_2430_MCBSP3_DX,
+
+	N3_2430_MCBSP4_CLKX,
+	AD23_2430_MCBSP4_DR,
+	AB25_2430_MCBSP4_DX,
+	AC25_2430_MCBSP4_FSX,
+
+	AE16_2430_MCBSP5_CLKX,
+	AF12_2430_MCBSP5_FSX,
+	K7_2430_MCBSP5_DX,
+	M1_2430_MCBSP5_DR,
+
+	/* 2430 McSPI*/
+	Y18_2430_MCSPI1_CLK,
+	AD15_2430_MCSPI1_SIMO,
+	AE17_2430_MCSPI1_SOMI,
+	U1_2430_MCSPI1_CS0,
+
+	/* Touchscreen GPIO */
+	AF19_2430_GPIO_85,
+
+};
+
+enum omap34xx_index {
+	/* 34xx I2C */
+	K21_34XX_I2C1_SCL,
+	J21_34XX_I2C1_SDA,
+	AF15_34XX_I2C2_SCL,
+	AE15_34XX_I2C2_SDA,
+	AF14_34XX_I2C3_SCL,
+	AG14_34XX_I2C3_SDA,
+	AD26_34XX_I2C4_SCL,
+	AE26_34XX_I2C4_SDA,
+
+	/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+	Y8_3430_USB1HS_PHY_CLK,
+	Y9_3430_USB1HS_PHY_STP,
+	AA14_3430_USB1HS_PHY_DIR,
+	AA11_3430_USB1HS_PHY_NXT,
+	W13_3430_USB1HS_PHY_DATA0,
+	W12_3430_USB1HS_PHY_DATA1,
+	W11_3430_USB1HS_PHY_DATA2,
+	Y11_3430_USB1HS_PHY_DATA3,
+	W9_3430_USB1HS_PHY_DATA4,
+	Y12_3430_USB1HS_PHY_DATA5,
+	W8_3430_USB1HS_PHY_DATA6,
+	Y13_3430_USB1HS_PHY_DATA7,
+
+	/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+	AA8_3430_USB2HS_PHY_CLK,
+	AA10_3430_USB2HS_PHY_STP,
+	AA9_3430_USB2HS_PHY_DIR,
+	AB11_3430_USB2HS_PHY_NXT,
+	AB10_3430_USB2HS_PHY_DATA0,
+	AB9_3430_USB2HS_PHY_DATA1,
+	W3_3430_USB2HS_PHY_DATA2,
+	T4_3430_USB2HS_PHY_DATA3,
+	T3_3430_USB2HS_PHY_DATA4,
+	R3_3430_USB2HS_PHY_DATA5,
+	R4_3430_USB2HS_PHY_DATA6,
+	T2_3430_USB2HS_PHY_DATA7,
+
+
+	/* TLL - HSUSB: 12-pin TLL Port 1*/
+	Y8_3430_USB1HS_TLL_CLK,
+	Y9_3430_USB1HS_TLL_STP,
+	AA14_3430_USB1HS_TLL_DIR,
+	AA11_3430_USB1HS_TLL_NXT,
+	W13_3430_USB1HS_TLL_DATA0,
+	W12_3430_USB1HS_TLL_DATA1,
+	W11_3430_USB1HS_TLL_DATA2,
+	Y11_3430_USB1HS_TLL_DATA3,
+	W9_3430_USB1HS_TLL_DATA4,
+	Y12_3430_USB1HS_TLL_DATA5,
+	W8_3430_USB1HS_TLL_DATA6,
+	Y13_3430_USB1HS_TLL_DATA7,
+
+	/* TLL - HSUSB: 12-pin TLL Port 2*/
+	AA8_3430_USB2HS_TLL_CLK,
+	AA10_3430_USB2HS_TLL_STP,
+	AA9_3430_USB2HS_TLL_DIR,
+	AB11_3430_USB2HS_TLL_NXT,
+	AB10_3430_USB2HS_TLL_DATA0,
+	AB9_3430_USB2HS_TLL_DATA1,
+	W3_3430_USB2HS_TLL_DATA2,
+	T4_3430_USB2HS_TLL_DATA3,
+	T3_3430_USB2HS_TLL_DATA4,
+	R3_3430_USB2HS_TLL_DATA5,
+	R4_3430_USB2HS_TLL_DATA6,
+	T2_3430_USB2HS_TLL_DATA7,
+
+	/* TLL - HSUSB: 12-pin TLL Port 3*/
+	AA6_3430_USB3HS_TLL_CLK,
+	AB3_3430_USB3HS_TLL_STP,
+	AA3_3430_USB3HS_TLL_DIR,
+	Y3_3430_USB3HS_TLL_NXT,
+	AA5_3430_USB3HS_TLL_DATA0,
+	Y4_3430_USB3HS_TLL_DATA1,
+	Y5_3430_USB3HS_TLL_DATA2,
+	W5_3430_USB3HS_TLL_DATA3,
+	AB12_3430_USB3HS_TLL_DATA4,
+	AB13_3430_USB3HS_TLL_DATA5,
+	AA13_3430_USB3HS_TLL_DATA6,
+	AA12_3430_USB3HS_TLL_DATA7,
+
+	/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
+	AF10_3430_USB1FS_PHY_MM1_RXDP,
+	AG9_3430_USB1FS_PHY_MM1_RXDM,
+	W13_3430_USB1FS_PHY_MM1_RXRCV,
+	W12_3430_USB1FS_PHY_MM1_TXSE0,
+	W11_3430_USB1FS_PHY_MM1_TXDAT,
+	Y11_3430_USB1FS_PHY_MM1_TXEN_N,
+
+	/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
+	AF7_3430_USB2FS_PHY_MM2_RXDP,
+	AH7_3430_USB2FS_PHY_MM2_RXDM,
+	AB10_3430_USB2FS_PHY_MM2_RXRCV,
+	AB9_3430_USB2FS_PHY_MM2_TXSE0,
+	W3_3430_USB2FS_PHY_MM2_TXDAT,
+	T4_3430_USB2FS_PHY_MM2_TXEN_N,
+
+	/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
+	AH3_3430_USB3FS_PHY_MM3_RXDP,
+	AE3_3430_USB3FS_PHY_MM3_RXDM,
+	AD1_3430_USB3FS_PHY_MM3_RXRCV,
+	AE1_3430_USB3FS_PHY_MM3_TXSE0,
+	AD2_3430_USB3FS_PHY_MM3_TXDAT,
+	AC1_3430_USB3FS_PHY_MM3_TXEN_N,
+
+	/* 34xx GPIO
+	 *  - normally these are bidirectional, no internal pullup/pulldown
+	 *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
+	 *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
+	 *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
+	 */
+	AH8_34XX_GPIO29,
+	J25_34XX_GPIO170,
 };
 
 struct omap_mux_cfg {