X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fplat-omap%2Finclude%2Fmach%2Fclock.h;h=073a2c5569f02c16969d95ce72451fa072692055;hb=eba05254cb561dc27d5664503f91f7c21954e648;hp=db57b71a67ba8974d8d8f9efb0a79b86006e3ada;hpb=ed99db8e5c53acced1a7c02aa9a94d50bea48409;p=linux-2.6-omap-h63xx.git diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index db57b71a67b..073a2c5569f 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -17,6 +17,11 @@ struct module; struct clk; struct clockdomain; +struct clkops { + int (*enable)(struct clk *); + void (*disable)(struct clk *); +}; + #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) struct clksel_rate { @@ -31,80 +36,61 @@ struct clksel { }; struct dpll_data { + void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; - unsigned long last_rounded_rate; - unsigned int rate_tolerance; - u32 max_tolerance; - struct clk *bypass_clk; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; u32 enable_mask; - u16 mult_div1_reg; - u16 control_reg; - u16 max_multiplier; + unsigned int rate_tolerance; + unsigned long last_rounded_rate; u16 last_rounded_m; u8 last_rounded_n; u8 min_divider; u8 max_divider; + u32 max_tolerance; + u16 max_multiplier; # if defined(CONFIG_ARCH_OMAP3) u8 modes; + void __iomem *autoidle_reg; + void __iomem *idlest_reg; + u32 autoidle_mask; + u32 freqsel_mask; + u32 idlest_mask; u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; - u16 autoidle_reg; - u16 idlest_reg; - u32 autoidle_mask; - u32 idlest_mask; - u32 freqsel_mask; # endif }; #endif -/** - * struct clk_child - used to track the children of a clock - * @clk: child struct clk * - * @node: list_head - * @flags: is this entry allocated in bootmem or slab? is it deleted? - * - * One struct clk_child is allocated for each child clock @clk of a - * parent clock. @flags values are listed below and start with CLK_CHILD_*. - */ -struct clk_child { - struct clk *clk; - struct list_head node; - u8 flags; -}; - struct clk { struct list_head node; + const struct clkops *ops; const char *name; int id; struct clk *parent; - unsigned long rate; - unsigned long temp_rate; struct list_head children; + struct list_head sibling; /* node for children */ + unsigned long rate; __u32 flags; - u32 enable_reg; - void (*recalc)(struct clk *, unsigned long, u8); + void __iomem *enable_reg; + unsigned long (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*init)(struct clk *); - int (*enable)(struct clk *); - void (*disable)(struct clk *); __u8 enable_bit; __s8 usecount; - u8 idlest_bit; #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) u8 fixed_div; + void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; struct dpll_data *dpll_data; - union { - const char *name; - struct clockdomain *ptr; - } clkdm; - u16 clksel_reg; - s16 prcm_mod; + const char *clkdm_name; + struct clockdomain *clkdm; #else __u8 rate_offset; __u8 src_offset; @@ -117,13 +103,11 @@ struct clk { struct cpufreq_frequency_table; struct clk_functions { - int (*clk_register)(struct clk *clk); int (*clk_enable)(struct clk *clk); void (*clk_disable)(struct clk *clk); long (*clk_round_rate)(struct clk *clk, unsigned long rate); int (*clk_set_rate)(struct clk *clk, unsigned long rate); int (*clk_set_parent)(struct clk *clk, struct clk *parent); - struct clk * (*clk_get_parent)(struct clk *clk); void (*clk_allow_idle)(struct clk *clk); void (*clk_deny_idle)(struct clk *clk); void (*clk_disable_unused)(struct clk *clk); @@ -135,70 +119,41 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); +extern void clk_init_one(struct clk *clk); extern int clk_register(struct clk *clk); +extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk, u8 rate_storage); +extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); -extern void followparent_recalc(struct clk *clk, unsigned long parent_rate, - u8 rate_storage); -extern void clk_allow_idle(struct clk *clk); -extern void clk_deny_idle(struct clk *clk); +extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); #ifdef CONFIG_CPU_FREQ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); #endif -void omap_clk_add_child(struct clk *clk, struct clk *clk2); -void omap_clk_del_child(struct clk *clk, struct clk *clk2); + +extern const struct clkops clkops_null; /* Clock flags */ -#define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ -/* bits 1-3 are currently free */ -#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ +/* bit 0 is free */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +/* bits 2-4 are free */ #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ -/* bit 6 is currently free */ #define CLOCK_IDLE_CONTROL (1 << 7) #define CLOCK_NO_IDLE_PARENT (1 << 8) #define DELAYED_APP (1 << 9) /* Delay application of clock */ -/* bit 10 is currently free */ +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -#define WAIT_READY (1 << 13) /* wait for dev to leave idle */ -#define RECALC_ON_ENABLE (1 << 14) /* recalc/prop on ena/disa */ -/* bits 15-20 are currently free */ -#define CLOCK_IN_OMAP310 (1 << 21) -#define CLOCK_IN_OMAP730 (1 << 22) -#define CLOCK_IN_OMAP1510 (1 << 23) -#define CLOCK_IN_OMAP16XX (1 << 24) -#define CLOCK_IN_OMAP242X (1 << 25) -#define CLOCK_IN_OMAP243X (1 << 26) -#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ -#define PARENT_CONTROLS_CLOCK (1 << 28) -#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ -#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2+ clocks only */ +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ +/* bits 13-31 are currently free */ /* Clksel_rate flags */ #define DEFAULT_RATE (1 << 0) #define RATE_IN_242X (1 << 1) #define RATE_IN_243X (1 << 2) #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ -#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2+ rates only */ +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) -/* rate_storage parameter flags */ -#define CURRENT_RATE 0 -#define TEMP_RATE 1 - -/* clk_child flags */ -#define CLK_CHILD_SLAB_ALLOC (1 << 0) /* if !set, bootmem was used */ -#define CLK_CHILD_DELETED (1 << 1) /* can be reused */ - -/* - * clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod - * is significant) - */ -#define PRCM_MOD_ADDR_MASK 0xff00 -#define CLK_REG_IN_PRM (1 << 0) -#define CLK_REG_IN_SCM (1 << 1) #endif