X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-omap2%2Fprm.h;h=826d326b8062d2e2177f0fbfdb3c72e25a88c324;hb=eba05254cb561dc27d5664503f91f7c21954e648;hp=3c6418e8e71a74745944fe84120482e9148f58ce;hpb=ed99db8e5c53acced1a7c02aa9a94d50bea48409;p=linux-2.6-omap-h63xx.git diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 3c6418e8e71..826d326b806 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Power/Reset Management (PRM) register definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007 Nokia Corporation * * Written by Paul Walmsley * @@ -16,16 +16,21 @@ #include "prcm-common.h" +#ifndef __ASSEMBLER__ +#define OMAP_PRM_REGADDR(module, reg) \ + IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) +#else #define OMAP2420_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) #define OMAP2430_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) #define OMAP34XX_PRM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) +#endif /* * Architecture-specific global PRM registers - * Use prm_{read,write}_mod_reg() with these registers. + * Use __raw_{read,write}l() with these registers. * * With a few exceptions, these are the register names beginning with * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the @@ -33,66 +38,80 @@ * */ -/* Common registers for 24xx and 34xx in OCP_MOD */ -#define OMAP2_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2_PRM_IRQENABLE_MPU_OFFSET 0x001c - -/* 24xx register offsets in OCP_MOD */ -#define OMAP24XX_PRM_REVISION_OFFSET 0x0000 -#define OMAP24XX_PRM_SYSCONFIG_OFFSET 0x0010 - -/* 34xx register offsets in OCP_MOD */ -#define OMAP3430_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_SYSCONFIG_OFFSET 0x0014 - -/* 24xx register offsets in OMAP24XX_GR_MOD (Same as OCP_MOD for 24xx) */ +/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */ #define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP24XX_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP24XX_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 #define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP24XX_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP24XX_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP24XX_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP24XX_PRCM_POLCTRL_OFFSET 0x0098 - -/* 34xx register offsets in GR_MOD */ -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 - -/* 34xx register offsets in CCR_MOD */ -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 + +/* 242x GR_MOD registers, use these only for assembly code */ +#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* 243x GR_MOD registers, use these only for assembly code */ +#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_VOLTCTRL_OFFSET) +#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \ + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET) + +/* These will disappear */ +#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) /* * Module specific PRM registers from PRM_BASE + domain offset @@ -146,6 +165,7 @@ #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + #ifndef __ASSEMBLER__ /* Power/reset management domain register get/set */