X-Git-Url: http://www.pilppa.org/gitweb/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-omap2%2Fclock34xx.h;h=f0090175d5972f7c9806f71e723db28ec1d250aa;hb=a0e7d508f6c9e00d1749353eb82db08dca178f41;hp=1ff05d351b3874f55479023eb93c593e8888e4a9;hpb=bc51da4ee46d481dc3fbc57ec407594b80e92705;p=linux-2.6-omap-h63xx.git diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 1ff05d351b3..f0090175d59 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -27,11 +27,14 @@ #include "prm.h" #include "prm-regbits-34xx.h" -static void omap3_dpll_recalc(struct clk *clk); -static void omap3_clkoutx2_recalc(struct clk *clk); +static unsigned long omap3_dpll_recalc(struct clk *clk); +static unsigned long omap3_clkoutx2_recalc(struct clk *clk); static void omap3_dpll_allow_idle(struct clk *clk); static void omap3_dpll_deny_idle(struct clk *clk); static u32 omap3_dpll_autoidle_read(struct clk *clk); +static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); +static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); +static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); /* Maximum DPLL multiplier, divider values for OMAP3 */ #define OMAP3_MAX_DPLL_MULT 2048 @@ -45,6 +48,10 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk); * DPLL5 supplies other peripheral clocks (USBHOST, USIM). */ +/* Forward declarations for DPLL bypass clocks */ +static struct clk dpll1_fck; +static struct clk dpll2_fck; + /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ #define DPLL_LOW_POWER_STOP 0x1 #define DPLL_LOW_POWER_BYPASS 0x5 @@ -57,16 +64,14 @@ static struct clk omap_32k_fck = { .name = "omap_32k_fck", .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk secure_32k_fck = { .name = "secure_32k_fck", .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; /* Virtual source clocks for osc_sys_ck */ @@ -74,48 +79,42 @@ static struct clk virt_12m_ck = { .name = "virt_12m_ck", .ops = &clkops_null, .rate = 12000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk virt_13m_ck = { .name = "virt_13m_ck", .ops = &clkops_null, .rate = 13000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk virt_16_8m_ck = { .name = "virt_16_8m_ck", .ops = &clkops_null, .rate = 16800000, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk virt_19_2m_ck = { .name = "virt_19_2m_ck", .ops = &clkops_null, .rate = 19200000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk virt_26m_ck = { .name = "virt_26m_ck", .ops = &clkops_null, .rate = 26000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static struct clk virt_38_4m_ck = { .name = "virt_38_4m_ck", .ops = &clkops_null, .rate = 38400000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, + .flags = RATE_FIXED, }; static const struct clksel_rate osc_sys_12m_rates[] = { @@ -168,7 +167,7 @@ static struct clk osc_sys_ck = { .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, .clksel = osc_sys_clksel, /* REVISIT: deal with autoextclkmode? */ - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, .recalc = &omap2_clksel_recalc, }; @@ -193,34 +192,28 @@ static struct clk sys_ck = { .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, .clksel_mask = OMAP_SYSCLKDIV_MASK, .clksel = sys_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; static struct clk sys_altclk = { .name = "sys_altclk", .ops = &clkops_null, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &propagate_rate, }; /* Optional external clock input for some McBSPs */ static struct clk mcbsp_clks = { .name = "mcbsp_clks", .ops = &clkops_null, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &propagate_rate, }; /* PRM EXTERNAL CLOCK OUTPUT */ static struct clk sys_clkout1 = { .name = "sys_clkout1", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &osc_sys_ck, .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -228,16 +221,6 @@ static struct clk sys_clkout1 = { /* CM CLOCKS */ -static const struct clksel_rate dpll_bypass_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate dpll_locked_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - static const struct clksel_rate div16_dpll_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 2, .val = 2, .flags = RATE_IN_343X }, @@ -265,6 +248,9 @@ static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .clk_bypass = &dpll1_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -274,8 +260,9 @@ static struct dpll_data dpll1_dd = { .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, + .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -285,8 +272,9 @@ static struct clk dpll1_ck = { .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll1_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll1_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -298,7 +286,7 @@ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", .ops = &clkops_null, .parent = &dpll1_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll1_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -320,7 +308,7 @@ static struct clk dpll1_x2m2_ck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -332,6 +320,9 @@ static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .clk_bypass = &dpll2_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | @@ -342,8 +333,9 @@ static struct dpll_data dpll2_dd = { .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, + .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -353,8 +345,9 @@ static struct clk dpll2_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll2_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll2_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -376,7 +369,7 @@ static struct clk dpll2_m2_ck = { OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll2_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -389,6 +382,9 @@ static struct dpll_data dpll3_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, @@ -396,7 +392,10 @@ static struct dpll_data dpll3_dd = { .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -406,8 +405,8 @@ static struct clk dpll3_ck = { .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll3_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, + .clkdm_name = "dpll3_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -419,7 +418,7 @@ static struct clk dpll3_x2_ck = { .name = "dpll3_x2_ck", .ops = &clkops_null, .parent = &dpll3_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -463,11 +462,7 @@ static const struct clksel div31_dpll3m2_clksel[] = { { .parent = NULL } }; -/* - * DPLL3 output M2 - * REVISIT: This DPLL output divider must be changed in SRAM, so until - * that code is ready, this should remain a 'read-only' clksel clock. - */ +/* DPLL3 output M2 - primary control point for CORE speed */ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", .ops = &clkops_null, @@ -476,42 +471,25 @@ static struct clk dpll3_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll3_clkdm", + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap3_core_dpll_m2_set_rate, .recalc = &omap2_clksel_recalc, }; -static const struct clksel core_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk core_ck = { .name = "core_ck", .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = core_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel dpll3_m2x2_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } + .parent = &dpll3_m2_ck, + .recalc = &followparent_recalc, }; static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = dpll3_m2x2_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, + .parent = &dpll3_x2_ck, + .clkdm_name = "dpll3_clkdm", + .recalc = &followparent_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ @@ -529,7 +507,7 @@ static struct clk dpll3_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -540,26 +518,17 @@ static struct clk dpll3_m3x2_ck = { .parent = &dpll3_m3_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel emu_core_alwon_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", .ops = &clkops_null, .parent = &dpll3_m3x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = emu_core_alwon_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, + .clkdm_name = "dpll3_clkdm", + .recalc = &followparent_recalc, }; /* DPLL4 */ @@ -569,6 +538,9 @@ static struct dpll_data dpll4_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), @@ -578,8 +550,9 @@ static struct dpll_data dpll4_dd = { .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, + .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -589,8 +562,9 @@ static struct clk dpll4_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll4_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_dpll4_set_rate, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -603,7 +577,7 @@ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", .ops = &clkops_null, .parent = &dpll4_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -621,7 +595,7 @@ static struct clk dpll4_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3430_DIV_96M_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -632,51 +606,55 @@ static struct clk dpll4_m2x2_ck = { .parent = &dpll4_m2_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel omap_96m_alwon_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - +/* + * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as + * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: + * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and + * CM_96K_(F)CLK. + */ static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", .ops = &clkops_null, .parent = &dpll4_m2x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = omap_96m_alwon_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; -static struct clk omap_96m_fck = { - .name = "omap_96m_fck", +static struct clk cm_96m_fck = { + .name = "cm_96m_fck", .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; -static const struct clksel cm_96m_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, +static const struct clksel_rate omap_96m_dpll_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel_rate omap_96m_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 0 } +}; + +static const struct clksel omap_96m_fck_clksel[] = { + { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, + { .parent = &sys_ck, .rates = omap_96m_sys_rates }, { .parent = NULL } }; -static struct clk cm_96m_fck = { - .name = "cm_96m_fck", +static struct clk omap_96m_fck = { + .name = "omap_96m_fck", .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, + .parent = &sys_ck, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = cm_96m_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_96M_MASK, + .clksel = omap_96m_fck_clksel, .recalc = &omap2_clksel_recalc, }; @@ -689,7 +667,7 @@ static struct clk dpll4_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -701,28 +679,11 @@ static struct clk dpll4_m3x2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel virt_omap_54m_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - -static struct clk virt_omap_54m_fck = { - .name = "virt_omap_54m_fck", - .ops = &clkops_null, - .parent = &dpll4_m3x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = virt_omap_54m_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, -}; - static const struct clksel_rate omap_54m_d4m3x2_rates[] = { { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 0 } @@ -734,7 +695,7 @@ static const struct clksel_rate omap_54m_alt_rates[] = { }; static const struct clksel omap_54m_clksel[] = { - { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, + { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, { .parent = NULL } }; @@ -744,13 +705,12 @@ static struct clk omap_54m_fck = { .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_54M, + .clksel_mask = OMAP3430_SOURCE_54M_MASK, .clksel = omap_54m_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; -static const struct clksel_rate omap_48m_96md2_rates[] = { +static const struct clksel_rate omap_48m_cm96m_rates[] = { { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 0 } }; @@ -761,7 +721,7 @@ static const struct clksel_rate omap_48m_alt_rates[] = { }; static const struct clksel omap_48m_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, + { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, { .parent = NULL } }; @@ -771,9 +731,8 @@ static struct clk omap_48m_fck = { .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_48M, + .clksel_mask = OMAP3430_SOURCE_48M_MASK, .clksel = omap_48m_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -782,7 +741,6 @@ static struct clk omap_12m_fck = { .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_fixed_divisor_recalc, }; @@ -795,8 +753,10 @@ static struct clk dpll4_m4_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ @@ -806,7 +766,8 @@ static struct clk dpll4_m4x2_ck = { .parent = &dpll4_m4_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -819,7 +780,7 @@ static struct clk dpll4_m5_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -830,7 +791,8 @@ static struct clk dpll4_m5x2_ck = { .parent = &dpll4_m5_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -843,7 +805,7 @@ static struct clk dpll4_m6_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -855,7 +817,8 @@ static struct clk dpll4_m6x2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -863,7 +826,7 @@ static struct clk emu_per_alwon_ck = { .name = "emu_per_alwon_ck", .ops = &clkops_null, .parent = &dpll4_m6x2_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "dpll4_clkdm", .recalc = &followparent_recalc, }; @@ -875,6 +838,9 @@ static struct dpll_data dpll5_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), @@ -884,8 +850,9 @@ static struct dpll_data dpll5_dd = { .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), - .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, + .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -895,8 +862,9 @@ static struct clk dpll5_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll5_dd, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "dpll5_clkdm", .recalc = &omap3_dpll_recalc, }; @@ -913,25 +881,7 @@ static struct clk dpll5_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel omap_120m_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - -static struct clk omap_120m_fck = { - .name = "omap_120m_fck", - .ops = &clkops_null, - .parent = &dpll5_m2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), - .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, - .clksel = omap_120m_fck_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, + .clkdm_name = "dpll5_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -958,23 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { }; static const struct clksel clkout2_src_clksel[] = { - { .parent = &core_ck, .rates = clkout2_src_core_rates }, - { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, - { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, - { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, + { .parent = &core_ck, .rates = clkout2_src_core_rates }, + { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, + { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, + { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, { .parent = NULL } }; static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, .enable_reg = OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clkdm_name = "core_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -999,7 +949,6 @@ static struct clk sys_clkout2 = { .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, - .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_clksel_recalc, }; @@ -1009,14 +958,20 @@ static struct clk corex2_fck = { .name = "corex2_fck", .ops = &clkops_null, .parent = &dpll3_m2x2_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; /* DPLL power domain clock controls */ -static const struct clksel div2_core_clksel[] = { - { .parent = &core_ck, .rates = div2_rates }, +static const struct clksel_rate div4_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, + { .div = 2, .val = 2, .flags = RATE_IN_343X }, + { .div = 4, .val = 4, .flags = RATE_IN_343X }, + { .div = 0 } +}; + +static const struct clksel div4_core_clksel[] = { + { .parent = &core_ck, .rates = div4_rates }, { .parent = NULL } }; @@ -1031,34 +986,16 @@ static struct clk dpll1_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, - .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clksel = div4_core_clksel, .recalc = &omap2_clksel_recalc, }; -/* - * MPU clksel: - * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck - * derives from the high-frequency bypass clock originating from DPLL3, - * called 'dpll1_fck' - */ -static const struct clksel mpu_clksel[] = { - { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, - { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk mpu_ck = { .name = "mpu_ck", .ops = &clkops_null, .parent = &dpll1_x2m2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, - .clksel = mpu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "mpu_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ @@ -1081,7 +1018,6 @@ static struct clk arm_fck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1095,7 +1031,6 @@ static struct clk emu_mpu_alwon_ck = { .name = "emu_mpu_alwon_ck", .ops = &clkops_null, .parent = &mpu_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1106,24 +1041,10 @@ static struct clk dpll2_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, - .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, + .clksel = div4_core_clksel, .recalc = &omap2_clksel_recalc, }; -/* - * IVA2 clksel: - * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck - * derives from the high-frequency bypass clock originating from DPLL3, - * called 'dpll2_fck' - */ - -static const struct clksel iva2_clksel[] = { - { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, - { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk iva2_ck = { .name = "iva2_ck", .ops = &clkops_omap2_dflt_wait, @@ -1131,17 +1052,17 @@ static struct clk iva2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, - OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, - .clksel = iva2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "iva2_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* Common interface clocks */ +static const struct clksel div2_core_clksel[] = { + { .parent = &core_ck, .rates = div2_rates }, + { .parent = NULL } +}; + static struct clk l3_ick = { .name = "l3_ick", .ops = &clkops_null, @@ -1150,7 +1071,6 @@ static struct clk l3_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1168,7 +1088,6 @@ static struct clk l4_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, @@ -1187,7 +1106,6 @@ static struct clk rm_ick = { .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_RM_MASK, .clksel = div2_l4_clksel, - .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_clksel_recalc, }; @@ -1208,7 +1126,6 @@ static struct clk gfx_l3_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .recalc = &followparent_recalc, }; @@ -1220,7 +1137,6 @@ static struct clk gfx_l3_fck = { .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, - .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1229,7 +1145,6 @@ static struct clk gfx_l3_ick = { .name = "gfx_l3_ick", .ops = &clkops_null, .parent = &gfx_l3_ck, - .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; @@ -1241,7 +1156,6 @@ static struct clk gfx_cg1_ck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; @@ -1253,7 +1167,6 @@ static struct clk gfx_cg2_ck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; @@ -1283,11 +1196,10 @@ static struct clk sgx_fck = { .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, + .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "sgx_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1298,8 +1210,7 @@ static struct clk sgx_ick = { .parent = &l3_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, + .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, .clkdm_name = "sgx_clkdm", .recalc = &followparent_recalc, }; @@ -1313,7 +1224,6 @@ static struct clk d2d_26m_fck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; @@ -1334,7 +1244,6 @@ static struct clk gpt10_fck = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1349,38 +1258,34 @@ static struct clk gpt11_fck = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk cpefuse_fck = { .name = "cpefuse_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, }; static struct clk ts_fck = { .name = "ts_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &omap_32k_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, }; static struct clk usbtll_fck = { .name = "usbtll_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &omap_120m_fck, + .ops = &clkops_omap2_dflt, + .parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .recalc = &followparent_recalc, }; @@ -1390,7 +1295,6 @@ static struct clk core_96m_fck = { .name = "core_96m_fck", .ops = &clkops_null, .parent = &omap_96m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1402,7 +1306,6 @@ static struct clk mmchs3_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1414,7 +1317,6 @@ static struct clk mmchs2_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1425,7 +1327,6 @@ static struct clk mspro_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1436,7 +1337,6 @@ static struct clk mmchs1_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1448,7 +1348,6 @@ static struct clk i2c3_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1460,7 +1359,6 @@ static struct clk i2c2_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1472,7 +1370,6 @@ static struct clk i2c1_fck = { .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1507,7 +1404,6 @@ static struct clk mcbsp5_fck = { .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, .clksel = mcbsp_15_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1522,7 +1418,6 @@ static struct clk mcbsp1_fck = { .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, .clksel = mcbsp_15_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1533,7 +1428,6 @@ static struct clk core_48m_fck = { .name = "core_48m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1545,7 +1439,6 @@ static struct clk mcspi4_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1556,7 +1449,6 @@ static struct clk mcspi3_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1567,7 +1459,6 @@ static struct clk mcspi2_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1578,7 +1469,6 @@ static struct clk mcspi1_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1588,7 +1478,6 @@ static struct clk uart2_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1598,7 +1487,6 @@ static struct clk uart1_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1608,7 +1496,6 @@ static struct clk fshostusb_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .recalc = &followparent_recalc, }; @@ -1618,7 +1505,6 @@ static struct clk core_12m_fck = { .name = "core_12m_fck", .ops = &clkops_null, .parent = &omap_12m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1629,7 +1515,6 @@ static struct clk hdq_fck = { .parent = &core_12m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1659,7 +1544,6 @@ static struct clk ssi_ssr_fck = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1669,7 +1553,6 @@ static struct clk ssi_sst_fck = { .ops = &clkops_null, .parent = &ssi_ssr_fck, .fixed_div = 2, - .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_fixed_divisor_recalc, }; @@ -1686,7 +1569,6 @@ static struct clk core_l3_ick = { .ops = &clkops_null, .parent = &l3_ick, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1697,7 +1579,6 @@ static struct clk hsotgusb_ick = { .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1708,7 +1589,7 @@ static struct clk sdrc_ick = { .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, - .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1717,7 +1598,7 @@ static struct clk gpmc_fck = { .name = "gpmc_fck", .ops = &clkops_null, .parent = &core_l3_ick, - .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */ + .flags = ENABLE_ON_INIT, /* huh? */ .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1728,7 +1609,6 @@ static struct clk security_l3_ick = { .name = "security_l3_ick", .ops = &clkops_null, .parent = &l3_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1738,7 +1618,6 @@ static struct clk pka_ick = { .parent = &security_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -1749,7 +1628,6 @@ static struct clk core_l4_ick = { .ops = &clkops_null, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1760,7 +1638,6 @@ static struct clk usbtll_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1772,7 +1649,6 @@ static struct clk mmchs3_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1784,7 +1660,6 @@ static struct clk icr_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1795,7 +1670,6 @@ static struct clk aes2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1806,7 +1680,6 @@ static struct clk sha12_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1817,7 +1690,6 @@ static struct clk des2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1829,7 +1701,6 @@ static struct clk mmchs2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1840,7 +1711,6 @@ static struct clk mmchs1_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1851,7 +1721,6 @@ static struct clk mspro_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1862,7 +1731,6 @@ static struct clk hdq_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1874,7 +1742,6 @@ static struct clk mcspi4_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1886,7 +1753,6 @@ static struct clk mcspi3_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1898,7 +1764,6 @@ static struct clk mcspi2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1910,7 +1775,6 @@ static struct clk mcspi1_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1922,7 +1786,6 @@ static struct clk i2c3_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1934,7 +1797,6 @@ static struct clk i2c2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1946,7 +1808,6 @@ static struct clk i2c1_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1957,7 +1818,6 @@ static struct clk uart2_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1968,7 +1828,6 @@ static struct clk uart1_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1979,7 +1838,6 @@ static struct clk gpt11_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1990,7 +1848,6 @@ static struct clk gpt10_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2002,7 +1859,6 @@ static struct clk mcbsp5_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2014,7 +1870,6 @@ static struct clk mcbsp1_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2025,7 +1880,6 @@ static struct clk fac_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, - .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2036,7 +1890,6 @@ static struct clk mailboxes_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2047,7 +1900,7 @@ static struct clk omapctrl_ick = { .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, - .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, + .flags = ENABLE_ON_INIT, .recalc = &followparent_recalc, }; @@ -2057,7 +1910,6 @@ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2068,7 +1920,6 @@ static struct clk ssi_ick = { .parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2091,7 +1942,6 @@ static struct clk usb_l4_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, .clksel = usb_l4_clksel, - .flags = CLOCK_IN_OMAP3430ES1, .recalc = &omap2_clksel_recalc, }; @@ -2103,7 +1953,6 @@ static struct clk security_l4_ick2 = { .name = "security_l4_ick2", .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2113,7 +1962,6 @@ static struct clk aes1_ick = { .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -2123,7 +1971,6 @@ static struct clk rng_ick = { .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -2133,7 +1980,6 @@ static struct clk sha11_ick = { .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -2143,30 +1989,18 @@ static struct clk des1_ick = { .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; /* DSS */ -static const struct clksel dss1_alwon_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", .ops = &clkops_omap2_dflt, .parent = &dpll4_m4x2_ck, - .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = dss1_alwon_fck_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk dss_tv_fck = { @@ -2176,7 +2010,6 @@ static struct clk dss_tv_fck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; @@ -2188,7 +2021,6 @@ static struct clk dss_96m_fck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; @@ -2200,7 +2032,6 @@ static struct clk dss2_alwon_fck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; @@ -2213,43 +2044,41 @@ static struct clk dss_ick = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; /* CAM */ -static const struct clksel cam_mclk_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk cam_mclk = { .name = "cam_mclk", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &dpll4_m5x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = cam_mclk_clksel, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "cam_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, - .flags = CLOCK_IN_OMAP343X, + .clkdm_name = "cam_clkdm", + .recalc = &followparent_recalc, +}; + +static struct clk csi2_96m_fck = { + .name = "csi2_96m_fck", + .ops = &clkops_omap2_dflt, + .parent = &core_96m_fck, + .init = &omap2_init_clk_clkdm, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CSI2_SHIFT, .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; @@ -2259,11 +2088,10 @@ static struct clk cam_ick = { static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", .ops = &clkops_omap2_dflt_wait, - .parent = &omap_120m_fck, + .parent = &dpll5_m2_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; @@ -2275,7 +2103,6 @@ static struct clk usbhost_48m_fck = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; @@ -2288,19 +2115,6 @@ static struct clk usbhost_ick = { .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_sar_fck = { - .name = "usbhost_sar_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &osc_sys_ck, - .init = &omap2_init_clk_clkdm, - .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), - .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; @@ -2325,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = { static const struct clksel usim_clksel[] = { { .parent = &omap_96m_fck, .rates = usim_96m_rates }, - { .parent = &omap_120m_fck, .rates = usim_120m_rates }, + { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, { .parent = &sys_ck, .rates = div2_rates }, { .parent = NULL }, }; @@ -2340,7 +2154,6 @@ static struct clk usim_fck = { .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, .clksel = usim_clksel, - .flags = CLOCK_IN_OMAP3430ES2, .recalc = &omap2_clksel_recalc, }; @@ -2354,7 +2167,6 @@ static struct clk gpt1_fck = { .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2364,7 +2176,6 @@ static struct clk wkup_32k_fck = { .ops = &clkops_null, .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2375,7 +2186,6 @@ static struct clk gpio1_dbck = { .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2386,7 +2196,6 @@ static struct clk wdt2_fck = { .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2395,7 +2204,6 @@ static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", .ops = &clkops_null, .parent = &sys_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2408,7 +2216,6 @@ static struct clk usim_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .flags = CLOCK_IN_OMAP3430ES2, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2419,7 +2226,6 @@ static struct clk wdt2_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2430,7 +2236,6 @@ static struct clk wdt1_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2441,7 +2246,6 @@ static struct clk gpio1_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2452,7 +2256,6 @@ static struct clk omap_32ksync_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2464,7 +2267,6 @@ static struct clk gpt12_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2475,7 +2277,6 @@ static struct clk gpt1_ick = { .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2489,7 +2290,6 @@ static struct clk per_96m_fck = { .ops = &clkops_null, .parent = &omap_96m_alwon_fck, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2499,7 +2299,6 @@ static struct clk per_48m_fck = { .ops = &clkops_null, .parent = &omap_48m_fck, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2510,7 +2309,6 @@ static struct clk uart3_fck = { .parent = &per_48m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2524,7 +2322,6 @@ static struct clk gpt2_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2538,7 +2335,6 @@ static struct clk gpt3_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2552,7 +2348,6 @@ static struct clk gpt4_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2566,7 +2361,6 @@ static struct clk gpt5_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2580,7 +2374,6 @@ static struct clk gpt6_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2594,7 +2387,6 @@ static struct clk gpt7_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2608,7 +2400,6 @@ static struct clk gpt8_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2622,7 +2413,6 @@ static struct clk gpt9_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel = omap343x_gpt_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2632,7 +2422,6 @@ static struct clk per_32k_alwon_fck = { .ops = &clkops_null, .parent = &omap_32k_fck, .clkdm_name = "per_clkdm", - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2642,7 +2431,6 @@ static struct clk gpio6_dbck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2653,7 +2441,6 @@ static struct clk gpio5_dbck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2664,7 +2451,6 @@ static struct clk gpio4_dbck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2675,7 +2461,6 @@ static struct clk gpio3_dbck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2686,7 +2471,6 @@ static struct clk gpio2_dbck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2697,7 +2481,6 @@ static struct clk wdt3_fck = { .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2706,7 +2489,6 @@ static struct clk per_l4_ick = { .name = "per_l4_ick", .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2717,7 +2499,6 @@ static struct clk gpio6_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2728,7 +2509,6 @@ static struct clk gpio5_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2739,7 +2519,6 @@ static struct clk gpio4_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2750,7 +2529,6 @@ static struct clk gpio3_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2761,7 +2539,6 @@ static struct clk gpio2_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2772,7 +2549,6 @@ static struct clk wdt3_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2783,7 +2559,6 @@ static struct clk uart3_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2794,7 +2569,6 @@ static struct clk gpt9_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2805,7 +2579,6 @@ static struct clk gpt8_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2816,7 +2589,6 @@ static struct clk gpt7_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2827,7 +2599,6 @@ static struct clk gpt6_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2838,7 +2609,6 @@ static struct clk gpt5_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2849,7 +2619,6 @@ static struct clk gpt4_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2860,7 +2629,6 @@ static struct clk gpt3_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2871,7 +2639,6 @@ static struct clk gpt2_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2883,7 +2650,6 @@ static struct clk mcbsp2_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2895,7 +2661,6 @@ static struct clk mcbsp3_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2907,14 +2672,13 @@ static struct clk mcbsp4_ick = { .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static const struct clksel mcbsp_234_clksel[] = { - { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, { .parent = NULL } }; @@ -2928,7 +2692,6 @@ static struct clk mcbsp2_fck = { .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2943,7 +2706,6 @@ static struct clk mcbsp3_fck = { .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2958,7 +2720,6 @@ static struct clk mcbsp4_fck = { .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, .clksel = mcbsp_234_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3007,7 +2768,6 @@ static struct clk emu_src_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3032,7 +2792,6 @@ static struct clk pclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3056,7 +2815,6 @@ static struct clk pclkx2_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3073,7 +2831,6 @@ static struct clk atclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3085,7 +2842,6 @@ static struct clk traceclk_src_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3109,7 +2865,6 @@ static struct clk traceclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3123,7 +2878,6 @@ static struct clk sr1_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -3134,7 +2888,6 @@ static struct clk sr2_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -3142,7 +2895,6 @@ static struct clk sr_l4_ick = { .name = "sr_l4_ick", .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -3154,7 +2906,6 @@ static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_null, .parent = &secure_32k_fck, - .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; @@ -3162,223 +2913,7 @@ static struct clk wdt1_fck = { .name = "wdt1_fck", .ops = &clkops_null, .parent = &secure_32k_fck, - .flags = CLOCK_IN_OMAP343X, - .recalc = &followparent_recalc, -}; - -static struct clk *onchip_34xx_clks[] __initdata = { - &omap_32k_fck, - &virt_12m_ck, - &virt_13m_ck, - &virt_16_8m_ck, - &virt_19_2m_ck, - &virt_26m_ck, - &virt_38_4m_ck, - &osc_sys_ck, - &sys_ck, - &sys_altclk, - &mcbsp_clks, - &sys_clkout1, - &dpll1_ck, - &dpll1_x2_ck, - &dpll1_x2m2_ck, - &dpll2_ck, - &dpll2_m2_ck, - &dpll3_ck, - &core_ck, - &dpll3_x2_ck, - &dpll3_m2_ck, - &dpll3_m2x2_ck, - &dpll3_m3_ck, - &dpll3_m3x2_ck, - &emu_core_alwon_ck, - &dpll4_ck, - &dpll4_x2_ck, - &omap_96m_alwon_fck, - &omap_96m_fck, - &cm_96m_fck, - &virt_omap_54m_fck, - &omap_54m_fck, - &omap_48m_fck, - &omap_12m_fck, - &dpll4_m2_ck, - &dpll4_m2x2_ck, - &dpll4_m3_ck, - &dpll4_m3x2_ck, - &dpll4_m4_ck, - &dpll4_m4x2_ck, - &dpll4_m5_ck, - &dpll4_m5x2_ck, - &dpll4_m6_ck, - &dpll4_m6x2_ck, - &emu_per_alwon_ck, - &dpll5_ck, - &dpll5_m2_ck, - &omap_120m_fck, - &clkout2_src_ck, - &sys_clkout2, - &corex2_fck, - &dpll1_fck, - &mpu_ck, - &arm_fck, - &emu_mpu_alwon_ck, - &dpll2_fck, - &iva2_ck, - &l3_ick, - &l4_ick, - &rm_ick, - &gfx_l3_ck, - &gfx_l3_fck, - &gfx_l3_ick, - &gfx_cg1_ck, - &gfx_cg2_ck, - &sgx_fck, - &sgx_ick, - &d2d_26m_fck, - &gpt10_fck, - &gpt11_fck, - &cpefuse_fck, - &ts_fck, - &usbtll_fck, - &core_96m_fck, - &mmchs3_fck, - &mmchs2_fck, - &mspro_fck, - &mmchs1_fck, - &i2c3_fck, - &i2c2_fck, - &i2c1_fck, - &mcbsp5_fck, - &mcbsp1_fck, - &core_48m_fck, - &mcspi4_fck, - &mcspi3_fck, - &mcspi2_fck, - &mcspi1_fck, - &uart2_fck, - &uart1_fck, - &fshostusb_fck, - &core_12m_fck, - &hdq_fck, - &ssi_ssr_fck, - &ssi_sst_fck, - &core_l3_ick, - &hsotgusb_ick, - &sdrc_ick, - &gpmc_fck, - &security_l3_ick, - &pka_ick, - &core_l4_ick, - &usbtll_ick, - &mmchs3_ick, - &icr_ick, - &aes2_ick, - &sha12_ick, - &des2_ick, - &mmchs2_ick, - &mmchs1_ick, - &mspro_ick, - &hdq_ick, - &mcspi4_ick, - &mcspi3_ick, - &mcspi2_ick, - &mcspi1_ick, - &i2c3_ick, - &i2c2_ick, - &i2c1_ick, - &uart2_ick, - &uart1_ick, - &gpt11_ick, - &gpt10_ick, - &mcbsp5_ick, - &mcbsp1_ick, - &fac_ick, - &mailboxes_ick, - &omapctrl_ick, - &ssi_l4_ick, - &ssi_ick, - &usb_l4_ick, - &security_l4_ick2, - &aes1_ick, - &rng_ick, - &sha11_ick, - &des1_ick, - &dss1_alwon_fck, - &dss_tv_fck, - &dss_96m_fck, - &dss2_alwon_fck, - &dss_ick, - &cam_mclk, - &cam_ick, - &usbhost_120m_fck, - &usbhost_48m_fck, - &usbhost_ick, - &usbhost_sar_fck, - &usim_fck, - &gpt1_fck, - &wkup_32k_fck, - &gpio1_dbck, - &wdt2_fck, - &wkup_l4_ick, - &usim_ick, - &wdt2_ick, - &wdt1_ick, - &gpio1_ick, - &omap_32ksync_ick, - &gpt12_ick, - &gpt1_ick, - &per_96m_fck, - &per_48m_fck, - &uart3_fck, - &gpt2_fck, - &gpt3_fck, - &gpt4_fck, - &gpt5_fck, - &gpt6_fck, - &gpt7_fck, - &gpt8_fck, - &gpt9_fck, - &per_32k_alwon_fck, - &gpio6_dbck, - &gpio5_dbck, - &gpio4_dbck, - &gpio3_dbck, - &gpio2_dbck, - &wdt3_fck, - &per_l4_ick, - &gpio6_ick, - &gpio5_ick, - &gpio4_ick, - &gpio3_ick, - &gpio2_ick, - &wdt3_ick, - &uart3_ick, - &gpt9_ick, - &gpt8_ick, - &gpt7_ick, - &gpt6_ick, - &gpt5_ick, - &gpt4_ick, - &gpt3_ick, - &gpt2_ick, - &mcbsp2_ick, - &mcbsp3_ick, - &mcbsp4_ick, - &mcbsp2_fck, - &mcbsp3_fck, - &mcbsp4_fck, - &emu_src_ck, - &pclk_fck, - &pclkx2_fck, - &atclk_fck, - &traceclk_src_fck, - &traceclk_fck, - &sr1_fck, - &sr2_fck, - &sr_l4_ick, - &secure_32k_fck, - &gpt12_fck, - &wdt1_fck, + .recalc = &followparent_recalc, }; #endif