Merge branch 'x86/unify-cpu-detect' into x86-v28-for-linus-phase4-D

[linux-2.6-omap-h63xx.git] / include / asm-x86 / cpufeature.h

diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 7bd98b724fd56b08219a7f67377a7af332a3f391..adfeae6586e175f9972012a94c823ede9527d0d1 100644 (file)
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -1,12 +1,12 @@
 /*
  * Defines x86 CPU feature bits
  */
-#ifndef _ASM_X86_CPUFEATURE_H
-#define _ASM_X86_CPUFEATURE_H
+#ifndef ASM_X86__CPUFEATURE_H
+#define ASM_X86__CPUFEATURE_H
 
 #include <asm/required-features.h>
 
-#define NCAPINTS       8       /* N 32-bit words worth of info */
+#define NCAPINTS       9       /* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -20,7 +20,7 @@
 #define X86_FEATURE_DE         (0*32+ 2) /* Debugging Extensions */
 #define X86_FEATURE_PSE                (0*32+ 3) /* Page Size Extensions */
 #define X86_FEATURE_TSC                (0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR                (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
+#define X86_FEATURE_MSR                (0*32+ 5) /* Model-Specific Registers */
 #define X86_FEATURE_PAE                (0*32+ 6) /* Physical Address Extensions */
 #define X86_FEATURE_MCE                (0*32+ 7) /* Machine Check Architecture */
 #define X86_FEATURE_CX8                (0*32+ 8) /* CMPXCHG8 instruction */
@@ -29,11 +29,12 @@
 #define X86_FEATURE_MTRR       (0*32+12) /* Memory Type Range Registers */
 #define X86_FEATURE_PGE                (0*32+13) /* Page Global Enable */
 #define X86_FEATURE_MCA                (0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV       (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
+#define X86_FEATURE_CMOV       (0*32+15) /* CMOV instructions */
+                                         /* (plus FCMOVcc, FCOMI with FPU) */
 #define X86_FEATURE_PAT                (0*32+16) /* Page Attribute Table */
 #define X86_FEATURE_PSE36      (0*32+17) /* 36-bit PSEs */
 #define X86_FEATURE_PN         (0*32+18) /* Processor serial number */
-#define X86_FEATURE_CLFLSH     (0*32+19) /* "clflush" Supports the CLFLUSH instruction */
+#define X86_FEATURE_CLFLSH     (0*32+19) /* "clflush" CLFLUSH instruction */
 #define X86_FEATURE_DS         (0*32+21) /* "dts" Debug Store */
 #define X86_FEATURE_ACPI       (0*32+22) /* ACPI via MSR */
 #define X86_FEATURE_MMX                (0*32+23) /* Multimedia Extensions */
@@ -79,15 +80,18 @@
 #define X86_FEATURE_UP         (3*32+ 9) /* smp kernel running on up */
 #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
+#define X86_FEATURE_NOPL       (3*32+20) /* The NOPL (0F 1F) instructions */
 #define X86_FEATURE_PEBS       (3*32+12) /* Precise-Event Based Sampling */
 #define X86_FEATURE_BTS                (3*32+13) /* Branch Trace Store */
 #define X86_FEATURE_SYSCALL32  (3*32+14) /* "" syscall in ia32 userspace */
 #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
-#define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this CPU */
+#define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well */
 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
 #define X86_FEATURE_11AP       (3*32+19) /* "" Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL       (3*32+20) /* The NOPL (0F 1F) instructions */
+#define X86_FEATURE_AMDC1E     (3*32+21) /* AMD C1E detected */
+#define X86_FEATURE_XTOPOLOGY  (3*32+21) /* cpu topology enum extensions */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* "pni" SSE-3 */
@@ -96,7 +100,7 @@
 #define X86_FEATURE_MWAIT      (4*32+ 3) /* "monitor" Monitor/Mwait support */
 #define X86_FEATURE_DSCPL      (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
 #define X86_FEATURE_VMX                (4*32+ 5) /* Hardware virtualization */
-#define X86_FEATURE_SMX                (4*32+ 6) /* "Safer" mode */
+#define X86_FEATURE_SMX                (4*32+ 6) /* Safer mode */
 #define X86_FEATURE_EST                (4*32+ 7) /* Enhanced SpeedStep */
 #define X86_FEATURE_TM2                (4*32+ 8) /* Thermal Monitor 2 */
 #define X86_FEATURE_SSSE3      (4*32+ 9) /* Supplemental SSE-3 */
@@ -148,6 +152,13 @@
  */
 #define X86_FEATURE_IDA                (7*32+ 0) /* Intel Dynamic Acceleration */
 
+/* Virtualization flags: Linux defined */
+#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
@@ -181,7 +192,7 @@ extern const char * const x86_power_flags[32];
 } while (0)
 #define setup_force_cpu_cap(bit) do { \
        set_cpu_cap(&boot_cpu_data, bit);       \
-       clear_bit(bit, (unsigned long *)cleared_cpu_caps);      \
+       clear_bit(bit, (unsigned long *)cleared_cpu_caps);      \
 } while (0)
 
 #define cpu_has_fpu            boot_cpu_has(X86_FEATURE_FPU)
@@ -257,4 +268,4 @@ extern const char * const x86_power_flags[32];
 
 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
 
-#endif /* _ASM_X86_CPUFEATURE_H */
+#endif /* ASM_X86__CPUFEATURE_H */