[POWERPC] spufs: use #defines for SPU class [012] exception status

[linux-2.6-omap-h63xx.git] / include / asm-powerpc / spu.h

diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 543c83c2dc62d68e3635e81d0dc813c7e0c3a149..816e3dc1f66f40478d760b9ca0d232011889712d 100644 (file)
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -527,8 +527,22 @@ struct spu_priv1 {
 #define CLASS2_ENABLE_SPU_STOP_INTR                    0x2L
 #define CLASS2_ENABLE_SPU_HALT_INTR                    0x4L
 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR  0x8L
+#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR           0x10L
        u8  pad_0x118_0x140[0x28];                              /* 0x118 */
        u64 int_stat_RW[3];                                     /* 0x140 */
+#define CLASS0_DMA_ALIGNMENT_INTR                      0x1L
+#define CLASS0_INVALID_DMA_COMMAND_INTR                        0x2L
+#define CLASS0_SPU_ERROR_INTR                          0x4L
+#define CLASS0_INTR_MASK                               0x7L
+#define CLASS1_SEGMENT_FAULT_INTR                      0x1L
+#define CLASS1_STORAGE_FAULT_INTR                      0x2L
+#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR          0x4L
+#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR          0x8L
+#define CLASS2_MAILBOX_INTR                            0x1L
+#define CLASS2_SPU_STOP_INTR                           0x2L
+#define CLASS2_SPU_HALT_INTR                           0x4L
+#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR         0x8L
+#define CLASS2_MAILBOX_THRESHOLD_INTR                  0x10L
        u8  pad_0x158_0x180[0x28];                              /* 0x158 */
        u64 int_route_RW;                                       /* 0x180 */