#ifndef __ASM_TX4927_TX4927_H
#define __ASM_TX4927_TX4927_H
-#include <asm/tx4927/tx4927_mips.h>
#include <asm/txx9irq.h>
-/*
- This register naming came from the integrated CPU/controller name TX4927
- followed by the device name from table 4.2.2 on page 4-3 and then followed
- by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul
- used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
- */
-
-#define TX4927_SIO_0_BASE
-
-/* TX4927 controller */
-#define TX4927_BASE 0xfff1f0000
-#define TX4927_BASE 0xfff1f0000
-#define TX4927_LIMIT 0xfff1fffff
-
-
-/* TX4927 SDRAM controller (64-bit registers) */
-#define TX4927_SDRAMC_BASE 0x8000
-#define TX4927_SDRAMC_SDCCR0 0x8000
-#define TX4927_SDRAMC_SDCCR1 0x8008
-#define TX4927_SDRAMC_SDCCR2 0x8010
-#define TX4927_SDRAMC_SDCCR3 0x8018
-#define TX4927_SDRAMC_SDCTR 0x8040
-#define TX4927_SDRAMC_SDCMD 0x8058
-#define TX4927_SDRAMC_LIMIT 0x8fff
-
-
-/* TX4927 external bus controller (64-bit registers) */
-#define TX4927_EBUSC_BASE 0x9000
-#define TX4927_EBUSC_EBCCR0 0x9000
-#define TX4927_EBUSC_EBCCR1 0x9008
-#define TX4927_EBUSC_EBCCR2 0x9010
-#define TX4927_EBUSC_EBCCR3 0x9018
-#define TX4927_EBUSC_EBCCR4 0x9020
-#define TX4927_EBUSC_EBCCR5 0x9028
-#define TX4927_EBUSC_EBCCR6 0x9030
-#define TX4927_EBUSC_EBCCR7 0x9008
-#define TX4927_EBUSC_LIMIT 0x9fff
-
-
-/* TX4927 SDRRAM Error Check Correction (64-bit registers) */
-#define TX4927_ECC_BASE 0xa000
-#define TX4927_ECC_ECCCR 0xa000
-#define TX4927_ECC_ECCSR 0xa008
-#define TX4927_ECC_LIMIT 0xafff
-
-
-/* TX4927 DMA Controller (64-bit registers) */
-#define TX4927_DMAC_BASE 0xb000
-#define TX4927_DMAC_TBD 0xb000
-#define TX4927_DMAC_LIMIT 0xbfff
-
-
-/* TX4927 PCI Controller (32-bit registers) */
-#define TX4927_PCIC_BASE 0xd000
-#define TX4927_PCIC_TBD 0xb000
-#define TX4927_PCIC_LIMIT 0xdfff
-
-
-/* TX4927 Configuration registers (64-bit registers) */
-#define TX4927_CONFIG_BASE 0xe000
-#define TX4927_CONFIG_CCFG 0xe000
-#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42
-#define TX4927_CONFIG_CCFG_WDRST BM_41_41
-#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40
-#define TX4927_CONFIG_CCFG_BCFG BM_39_32
-#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27
-#define TX4927_CONFIG_CCFG_GTOT BM_26_25
-#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25
-#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26
-#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25
-#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25)
-#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24
-#define TX4927_CONFIG_CCFG_PCI66 BM_23_23
-#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22
-#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20
-#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17
-#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19
-#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17)
-#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18
-#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17
-#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17)
-#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17
-#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18
-#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17
-#define TX4927_CONFIG_CCFG_BEOW BM_16_16
-#define TX4927_CONFIG_CCFG_WR BM_15_15
-#define TX4927_CONFIG_CCFG_TOE BM_14_14
-#define TX4927_CONFIG_CCFG_PCIARB BM_13_13
-#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11
-#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08
-#define TX4927_CONFIG_CCFG_SYSSP BM_07_06
-#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03
-#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02
-#define TX4927_CONFIG_CCFG_ARMODE BM_01_01
-#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00
-#define TX4927_CONFIG_REVID 0xe008
-#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63
-#define TX4927_CONFIG_REVID_PCODE BM_16_31
-#define TX4927_CONFIG_REVID_MJERREV BM_12_15
-#define TX4927_CONFIG_REVID_MINEREV BM_08_11
-#define TX4927_CONFIG_REVID_MJREV BM_04_07
-#define TX4927_CONFIG_REVID_MINREV BM_00_03
-#define TX4927_CONFIG_PCFG 0xe010
-#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63
-#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56
-#define TX4927_CONFIG_PCFG_DRVCB BM_55_55
-#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54
-#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53
-#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52
-#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51
-#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50
-#define TX4927_CONFIG_PCFG_DRVWE BM_49_49
-#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48
-#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47
-#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k
-#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45
-#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44
-#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43
-#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42
-#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41
-#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40
-#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39
-#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32
-#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31
-#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29
-#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29)
-#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28
-#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29
-#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29
-#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27
-#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26
-#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25
-#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24
-#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23
-#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22
-#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21
-#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20
-#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19
-#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18
-#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17
-#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16
-#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15
-#define TX4927_CONFIG_PCFG_SEL2 BM_09_09
-#define TX4927_CONFIG_PCFG_SEL1 BM_08_08
-#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07
-#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07)
-#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06
-#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07
-#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07
-#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07)
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07)
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07
-#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07
-#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03
-#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03)
-#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02
-#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03
-#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03
-#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01
-#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01)
-#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00
-#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01
-#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01
-#define TX4927_CONFIG_TOEA 0xe018
-#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63
-#define TX4927_CONFIG_TOEA_TOEA BM_00_35
-#define TX4927_CONFIG_CLKCTR 0xe020
-#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63
-#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25
-#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24
-#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23
-#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22
-#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21
-#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20
-#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19
-#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18
-#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17
-#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16
-#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15
-#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09
-#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08
-#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07
-#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06
-#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05
-#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04
-#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03
-#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02
-#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01
-#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00
-#define TX4927_CONFIG_GARBC 0xe030
-#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63
-#define TX4927_CONFIG_GARBC_SET_09 BM_09_09
-#define TX4927_CONFIG_GARBC_ARBMD BM_08_08
-#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07
-#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05
-#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05)
-#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04
-#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05
-#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05
-#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03
-#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03)
-#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02
-#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03
-#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03
-#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01
-#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01)
-#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00
-#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01
-#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01
-#define TX4927_CONFIG_RAMP 0xe048
-#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63
-#define TX4927_CONFIG_RAMP_RAMP BM_00_19
-#define TX4927_CONFIG_LIMIT 0xefff
-
-
-/* TX4927 Timer 0 (32-bit registers) */
-#define TX4927_TMR0_BASE 0xf000
-#define TX4927_TMR0_TMTCR0 0xf000
-#define TX4927_TMR0_TMTISR0 0xf004
-#define TX4927_TMR0_TMCPRA0 0xf008
-#define TX4927_TMR0_TMCPRB0 0xf00c
-#define TX4927_TMR0_TMITMR0 0xf010
-#define TX4927_TMR0_TMCCDR0 0xf020
-#define TX4927_TMR0_TMPGMR0 0xf030
-#define TX4927_TMR0_TMTRR0 0xf0f0
-#define TX4927_TMR0_LIMIT 0xf0ff
-
-
-/* TX4927 Timer 1 (32-bit registers) */
-#define TX4927_TMR1_BASE 0xf100
-#define TX4927_TMR1_TMTCR1 0xf100
-#define TX4927_TMR1_TMTISR1 0xf104
-#define TX4927_TMR1_TMCPRA1 0xf108
-#define TX4927_TMR1_TMCPRB1 0xf10c
-#define TX4927_TMR1_TMITMR1 0xf110
-#define TX4927_TMR1_TMCCDR1 0xf120
-#define TX4927_TMR1_TMPGMR1 0xf130
-#define TX4927_TMR1_TMTRR1 0xf1f0
-#define TX4927_TMR1_LIMIT 0xf1ff
-
-
-/* TX4927 Timer 2 (32-bit registers) */
-#define TX4927_TMR2_BASE 0xf200
-#define TX4927_TMR2_TMTCR2 0xf200
-#define TX4927_TMR2_TMTISR2 0xf204
-#define TX4927_TMR2_TMCPRA2 0xf208
-#define TX4927_TMR2_TMITMR2 0xf210
-#define TX4927_TMR2_TMCCDR2 0xf220
-#define TX4927_TMR2_TMWTMR2 0xf240
-#define TX4927_TMR2_TMTRR2 0xf2f0
-#define TX4927_TMR2_LIMIT 0xf2ff
-
-
-/* TX4927 serial port 0 (32-bit registers) */
-#define TX4927_SIO0_BASE 0xf300
-#define TX4927_SIO0_SILCR0 0xf300
-#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
-#define TX4927_SIO0_SILCR0_RWUB BM_15_15
-#define TX4927_SIO0_SILCR0_TWUB BM_14_14
-#define TX4927_SIO0_SILCR0_UODE BM_13_13
-#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12
-#define TX4927_SIO0_SILCR0_SCS BM_05_06
-#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06)
-#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05
-#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06
-#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06
-#define TX4927_SIO0_SILCR0_UEPS BM_04_04
-#define TX4927_SIO0_SILCR0_UPEN BM_03_03
-#define TX4927_SIO0_SILCR0_USBL BM_02_02
-#define TX4927_SIO0_SILCR0_UMODE BM_00_01
-#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01
-#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
-#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
-#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
-#define TX4927_SIO0_SIDICR0 0xf304
-#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
-#define TX4927_SIO0_SIDICR0_TDE BM_15_15
-#define TX4927_SIO0_SIDICR0_RDE BM_14_14
-#define TX4927_SIO0_SIDICR0_TIE BM_13_13
-#define TX4927_SIO0_SIDICR0_RIE BM_12_12
-#define TX4927_SIO0_SIDICR0_SPIE BM_11_11
-#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10
-#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10)
-#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09
-#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10
-#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10
-#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08
-#define TX4927_SIO0_SIDICR0_STIE BM_00_05
-#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05)
-#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05
-#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04
-#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03
-#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
-#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
-#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
-#define TX4927_SIO0_SIDISR0 0xf308
-#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
-#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
-#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
-#define TX4927_SIO0_SIDISR0_UFER BM_13_13
-#define TX4927_SIO0_SIDISR0_UPER BM_12_12
-#define TX4927_SIO0_SIDISR0_UOER BM_11_11
-#define TX4927_SIO0_SIDISR0_ERI BM_10_10
-#define TX4927_SIO0_SIDISR0_TOUT BM_09_09
-#define TX4927_SIO0_SIDISR0_TDIS BM_08_08
-#define TX4927_SIO0_SIDISR0_RDIS BM_07_07
-#define TX4927_SIO0_SIDISR0_STIS BM_06_06
-#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
-#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
-#define TX4927_SIO0_SISCISR0 0xf30c
-#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
-#define TX4927_SIO0_SISCISR0_OERS BM_05_05
-#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
-#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03
-#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
-#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
-#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
-#define TX4927_SIO0_SIFCR0 0xf310
-#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
-#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
-#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
-#define TX4927_SIO0_SIFCR0_RDIL BM_16_31
-#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08)
-#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07
-#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08
-#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08
-#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06
-#define TX4927_SIO0_SIFCR0_TDIL BM_03_04
-#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04)
-#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03
-#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04
-#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04
-#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
-#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
-#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
-#define TX4927_SIO0_SIFLCR0 0xf314
-#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
-#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
-#define TX4927_SIO0_SIFLCR0_TES BM_11_11
-#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10
-#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09
-#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08
-#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07
-#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
-#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
-#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
-#define TX4927_SIO0_SIBGR0 0xf318
-#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
-#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
-#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
-#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08
-#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
-#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
-#define TX4927_SIO0_SIBGR0_BRD BM_00_07
-#define TX4927_SIO0_SITFIF00 0xf31c
-#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
-#define TX4927_SIO0_SITFIF00_TXD BM_00_07
-#define TX4927_SIO0_SIRFIFO0 0xf320
-#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
-#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
-#define TX4927_SIO0_SIRFIFO0 0xf320
-#define TX4927_SIO0_LIMIT 0xf3ff
-
-
-/* TX4927 serial port 1 (32-bit registers) */
-#define TX4927_SIO1_BASE 0xf400
-#define TX4927_SIO1_SILCR1 0xf400
-#define TX4927_SIO1_SIDICR1 0xf404
-#define TX4927_SIO1_SIDISR1 0xf408
-#define TX4927_SIO1_SISCISR1 0xf40c
-#define TX4927_SIO1_SIFCR1 0xf410
-#define TX4927_SIO1_SIFLCR1 0xf414
-#define TX4927_SIO1_SIBGR1 0xf418
-#define TX4927_SIO1_SITFIF01 0xf41c
-#define TX4927_SIO1_SIRFIFO1 0xf420
-#define TX4927_SIO1_LIMIT 0xf4ff
-
-
-/* TX4927 parallel port (32-bit registers) */
-#define TX4927_PIO_BASE 0xf500
-#define TX4927_PIO_PIOD0 0xf500
-#define TX4927_PIO_PIODI 0xf504
-#define TX4927_PIO_PIODIR 0xf508
-#define TX4927_PIO_PIOOD 0xf50c
-#define TX4927_PIO_LIMIT 0xf50f
-
-
-/* TX4927 AC-link controller (32-bit registers) */
-#define TX4927_ACLC_BASE 0xf700
-#define TX4927_ACLC_ACCTLEN 0xf700
-#define TX4927_ACLC_ACCTLDIS 0xf704
-#define TX4927_ACLC_ACREGACC 0xf708
-#define TX4927_ACLC_ACINTSTS 0xf710
-#define TX4927_ACLC_ACINTMSTS 0xf714
-#define TX4927_ACLC_ACINTEN 0xf718
-#define TX4927_ACLC_ACINTDIS 0xf71c
-#define TX4927_ACLC_ACSEMAPH 0xf720
-#define TX4927_ACLC_ACGPIDAT 0xf740
-#define TX4927_ACLC_ACGPODAT 0xf744
-#define TX4927_ACLC_ACSLTEN 0xf748
-#define TX4927_ACLC_ACSLTDIS 0xf74c
-#define TX4927_ACLC_ACFIFOSTS 0xf750
-#define TX4927_ACLC_ACDMASTS 0xf780
-#define TX4927_ACLC_ACDMASEL 0xf784
-#define TX4927_ACLC_ACAUDODAT 0xf7a0
-#define TX4927_ACLC_ACSURRDAT 0xf7a4
-#define TX4927_ACLC_ACCENTDAT 0xf7a8
-#define TX4927_ACLC_ACLFEDAT 0xf7ac
-#define TX4927_ACLC_ACAUDIDAT 0xf7b0
-#define TX4927_ACLC_ACMODODAT 0xf7b8
-#define TX4927_ACLC_ACMODIDAT 0xf7bc
-#define TX4927_ACLC_ACREVID 0xf7fc
-#define TX4927_ACLC_LIMIT 0xf7ff
-
-
-#define TX4927_REG(x) ((TX4927_BASE)+(x))
-
-#define TX4927_RD08( reg ) (*(vu08*)(reg))
-#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val))
-
-#define TX4927_RD16( reg ) (*(vu16*)(reg))
-#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val))
-
-#define TX4927_RD32( reg ) (*(vu32*)(reg))
-#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val))
-
-#define TX4927_RD64( reg ) (*(vu64*)(reg))
-#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val))
-
-#define TX4927_RD( reg ) TX4927_RD32( reg )
-#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
-
-
#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
-#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
-#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
+#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
+#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
-#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
+#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
+#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_WR 0x00008000
+#define TX4927_CCFG_TINTDIS 0x01000000
+
+#define TX4927_PCIMEM 0x08000000
+#define TX4927_PCIMEM_SIZE 0x08000000
+#define TX4927_PCIIO 0x16000000
+#define TX4927_PCIIO_SIZE 0x01000000
+
+#define TX4927_SDRAMC_REG 0xff1f8000
+#define TX4927_EBUSC_REG 0xff1f9000
+#define TX4927_PCIC_REG 0xff1fd000
+#define TX4927_CCFG_REG 0xff1fe000
+#define TX4927_IRC_REG 0xff1ff600
+#define TX4927_NR_TMR 3
+#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
+
+/* bits for ISTAT3/IMASK3/IMSTAT3 */
+#define TX4927_INT3B_PCID 0
+#define TX4927_INT3B_PCIC 1
+#define TX4927_INT3B_PCIB 2
+#define TX4927_INT3B_PCIA 3
+#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
+#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
+#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
+#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
+
+#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
+#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
+
+#define TX4927_IR_PCIC 16
+#define TX4927_IR_PCIERR 22
+#define TX4927_IR_PCIPMA 23
+#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
+#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
+#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
+#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
+#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
+#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
+#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
+
+#ifdef _LANGUAGE_ASSEMBLY
+#define _CONST64(c) c
+#else
+#define _CONST64(c) c##ull
+
+#include <asm/byteorder.h>
+
+struct tx4927_sdramc_reg {
+ volatile unsigned long long cr[4];
+ volatile unsigned long long unused0[4];
+ volatile unsigned long long tr;
+ volatile unsigned long long unused1[2];
+ volatile unsigned long long cmd;
+};
+
+struct tx4927_ebusc_reg {
+ volatile unsigned long long cr[8];
+};
+
+struct tx4927_ccfg_reg {
+ volatile unsigned long long ccfg;
+ volatile unsigned long long crir;
+ volatile unsigned long long pcfg;
+ volatile unsigned long long tear;
+ volatile unsigned long long clkctr;
+ volatile unsigned long long unused0;
+ volatile unsigned long long garbc;
+ volatile unsigned long long unused1;
+ volatile unsigned long long unused2;
+ volatile unsigned long long ramp;
+};
+
+struct tx4927_pcic_reg {
+ volatile unsigned long pciid;
+ volatile unsigned long pcistatus;
+ volatile unsigned long pciccrev;
+ volatile unsigned long pcicfg1;
+ volatile unsigned long p2gm0plbase; /* +10 */
+ volatile unsigned long p2gm0pubase;
+ volatile unsigned long p2gm1plbase;
+ volatile unsigned long p2gm1pubase;
+ volatile unsigned long p2gm2pbase; /* +20 */
+ volatile unsigned long p2giopbase;
+ volatile unsigned long unused0;
+ volatile unsigned long pcisid;
+ volatile unsigned long unused1; /* +30 */
+ volatile unsigned long pcicapptr;
+ volatile unsigned long unused2;
+ volatile unsigned long pcicfg2;
+ volatile unsigned long g2ptocnt; /* +40 */
+ volatile unsigned long unused3[15];
+ volatile unsigned long g2pstatus; /* +80 */
+ volatile unsigned long g2pmask;
+ volatile unsigned long pcisstatus;
+ volatile unsigned long pcimask;
+ volatile unsigned long p2gcfg; /* +90 */
+ volatile unsigned long p2gstatus;
+ volatile unsigned long p2gmask;
+ volatile unsigned long p2gccmd;
+ volatile unsigned long unused4[24]; /* +a0 */
+ volatile unsigned long pbareqport; /* +100 */
+ volatile unsigned long pbacfg;
+ volatile unsigned long pbastatus;
+ volatile unsigned long pbamask;
+ volatile unsigned long pbabm; /* +110 */
+ volatile unsigned long pbacreq;
+ volatile unsigned long pbacgnt;
+ volatile unsigned long pbacstate;
+ volatile unsigned long long g2pmgbase[3]; /* +120 */
+ volatile unsigned long long g2piogbase;
+ volatile unsigned long g2pmmask[3]; /* +140 */
+ volatile unsigned long g2piomask;
+ volatile unsigned long long g2pmpbase[3]; /* +150 */
+ volatile unsigned long long g2piopbase;
+ volatile unsigned long pciccfg; /* +170 */
+ volatile unsigned long pcicstatus;
+ volatile unsigned long pcicmask;
+ volatile unsigned long unused5;
+ volatile unsigned long long p2gmgbase[3]; /* +180 */
+ volatile unsigned long long p2giogbase;
+ volatile unsigned long g2pcfgadrs; /* +1a0 */
+ volatile unsigned long g2pcfgdata;
+ volatile unsigned long unused6[8];
+ volatile unsigned long g2pintack;
+ volatile unsigned long g2pspc;
+ volatile unsigned long unused7[12]; /* +1d0 */
+ volatile unsigned long long pdmca; /* +200 */
+ volatile unsigned long long pdmga;
+ volatile unsigned long long pdmpa;
+ volatile unsigned long long pdmcut;
+ volatile unsigned long long pdmcnt; /* +220 */
+ volatile unsigned long long pdmsts;
+ volatile unsigned long long unused8[2];
+ volatile unsigned long long pdmdb[4]; /* +240 */
+ volatile unsigned long long pdmtdh; /* +260 */
+ volatile unsigned long long pdmdms;
+};
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+/*
+ * PCIC
+ */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
+#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
+#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST 0x00000800
+#define TX4927_PCIC_PCICCFG_SRST 0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
+#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
+#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
+#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
+#define TX4927_PCIC_PCICCFG_IISE 0x00000020
+#define TX4927_PCIC_PCICCFG_ATR 0x00000010
+#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
+#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
+#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_PCI66 0x00800000
+#define TX4927_CCFG_PCIMIDE 0x00400000
+#define TX4927_CCFG_PCIXARB 0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
+
+#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
+#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
+#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
+#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
+#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
+#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
+#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
+#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
+#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_PCICKD 0x00400000
+#define TX4927_CLKCTR_PCIRST 0x00000040
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
#endif /* __ASM_TX4927_TX4927_H */
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