[MIPS] Pb1550 code style cleanup

[linux-2.6-omap-h63xx.git] / include / asm-mips / mach-pb1x00 / pb1550.h

diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index c2ab0e2df4ae1f20d3d1ec294ef8dfb7bea0455b..6704a11497dbd701cccb62bdc822625ade559ac6 100644 (file)
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -30,15 +30,15 @@
 #include <linux/types.h>
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+#define DBDMA_AC97_TX_CHAN     DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN     DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN      DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN      DSCR_CMD0_PSC3_RX
 
-#define SPI_PSC_BASE        PSC0_BASE_ADDR
-#define AC97_PSC_BASE       PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE      PSC2_BASE_ADDR
-#define I2S_PSC_BASE        PSC3_BASE_ADDR
+#define SPI_PSC_BASE           PSC0_BASE_ADDR
+#define AC97_PSC_BASE          PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE         PSC2_BASE_ADDR
+#define I2S_PSC_BASE           PSC3_BASE_ADDR
 
 #define BCSR_PHYS_ADDR 0xAF000000
 
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
 #define BCSR_SYSTEM_POWEROFF   0x4000
 #define BCSR_SYSTEM_RESET      0x8000
 
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
 
 /* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
-       ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+       ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
 
 #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 #define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
 #define PB1550_USER_ONLY
 #endif
 
-/* Timing values as described in databook, * ns value stripped of
+/*
+ * Timing values as described in databook, * ns value stripped of
  * lower 2 bits.
  * These defines are here rather than an SOC1550 generic file because
  * the parts chosen on another board may be different and may require
  * different timings.
  */
-#define NAND_T_H                       (18 >> 2)
-#define NAND_T_PUL                     (30 >> 2)
-#define NAND_T_SU                      (30 >> 2)
-#define NAND_T_WH                      (30 >> 2)
+#define NAND_T_H               (18 >> 2)
+#define NAND_T_PUL             (30 >> 2)
+#define NAND_T_SU              (30 >> 2)
+#define NAND_T_WH              (30 >> 2)
 
 /* Bitfield shift amounts */
 #define NAND_T_H_SHIFT         0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
 #define NAND_T_SU_SHIFT                8
 #define NAND_T_WH_SHIFT                12
 
-#define NAND_TIMING    ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
-                       ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
-                       ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
-                       ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+#define NAND_TIMING    (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
 
 #define NAND_CS 1
 
-/* should be done by yamon */
-#define NAND_STCFG  0x00400005 /* 8-bit NAND */
-#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
-#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
+/* Should be done by YAMON */
+#define NAND_STCFG     0x00400005 /* 8-bit NAND */
+#define NAND_STTIME    0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR    0x12000FFF /* physical address 0x20000000 */
 
 #endif /* __ASM_PB1550_H */