[MIPS] Pb1200/DBAu1200 code style cleanup

[linux-2.6-omap-h63xx.git] / include / asm-mips / mach-pb1x00 / pb1200.h

diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b4279933ed4b1419f92f35f972f4ddb..c8618df88cb51abedc40b29cd4468f61d2505f6c 100644 (file)
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
 /*
- * AMD Alchemy PB1200 Referrence Board
+ * AMD Alchemy Pb1200 Referrence Board
  * Board Registers defines.
  *
  * ########################################################################
@@ -27,21 +27,20 @@
 #include <linux/types.h>
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
-// This is defined in au1000.h with bogus value
-#undef AU1X00_EXTERNAL_INT
+#define DBDMA_AC97_TX_CHAN     DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN     DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN      DSCR_CMD0_PSC1_RX
 
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-
-/* SPI and SMB are muxed on the Pb1200 board.
-   Refer to board documentation.
+/*
+ * SPI and SMB are muxed on the Pb1200 board.
+ * Refer to board documentation.
  */
-#define SPI_PSC_BASE        PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE      PSC0_BASE_ADDR
-/* AC97 and I2S are muxed on the Pb1200 board.
-   Refer to board documentation.
+#define SPI_PSC_BASE           PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE         PSC0_BASE_ADDR
+/*
+ * AC97 and I2S are muxed on the Pb1200 board.
+ * Refer to board documentation.
  */
 #define AC97_PSC_BASE       PSC1_BASE_ADDR
 #define I2S_PSC_BASE           PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define BCSR_STATUS_SWAPBOOT   0x0040
 #define BCSR_STATUS_FLASHBUSY  0x0100
 #define BCSR_STATUS_IDECBLID   0x0200
-#define BCSR_STATUS_SD0WP              0x0400
-#define BCSR_STATUS_SD1WP              0x0800
-#define BCSR_STATUS_U0RXD              0x1000
-#define BCSR_STATUS_U1RXD              0x2000
+#define BCSR_STATUS_SD0WP      0x0400
+#define BCSR_STATUS_SD1WP      0x0800
+#define BCSR_STATUS_U0RXD      0x1000
+#define BCSR_STATUS_U1RXD      0x2000
 
 #define BCSR_SWITCHES_OCTAL    0x00FF
 #define BCSR_SWITCHES_DIP_1    0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define BCSR_RESETS_DC         0x0004
 #define BCSR_RESETS_IDE                0x0008
 /* not resets but in the same register */
-#define BCSR_RESETS_WSCFSM  0x0800
+#define BCSR_RESETS_WSCFSM     0x0800
 #define BCSR_RESETS_PCS0MUX    0x1000
 #define BCSR_RESETS_PCS1MUX    0x2000
 #define BCSR_RESETS_SPISEL     0x4000
-#define BCSR_RESETS_SD1MUX  0x8000
+#define BCSR_RESETS_SD1MUX     0x8000
 
 #define BCSR_PCMCIA_PC0VPP     0x0003
 #define BCSR_PCMCIA_PC0VCC     0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define BCSR_INT_PC0STSCHG     0x0008
 #define BCSR_INT_PC1           0x0010
 #define BCSR_INT_PC1STSCHG     0x0020
-#define BCSR_INT_DC                    0x0040
+#define BCSR_INT_DC            0x0040
 #define BCSR_INT_FLASHBUSY     0x0080
 #define BCSR_INT_PC0INSERT     0x0100
 #define BCSR_INT_PC0EJECT      0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define BCSR_INT_SD1INSERT     0x4000
 #define BCSR_INT_SD1EJECT      0x8000
 
-/* PCMCIA Db1x00 specific defines */
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
-       ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
-
 #define SMC91C111_PHYS_ADDR    0x0D000300
 #define SMC91C111_INT          PB1200_ETH_INT
 
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define IDE_DDMA_REQ           DSCR_CMD0_DMA_REQ1
 #define IDE_RQSIZE             128
 
-#define NAND_PHYS_ADDR   0x1C000000
+#define NAND_PHYS_ADDR         0x1C000000
 
-/* Timing values as described in databook, * ns value stripped of
+/*
+ * Timing values as described in databook, * ns value stripped of
  * lower 2 bits.
- * These defines are here rather than an SOC1200 generic file because
+ * These defines are here rather than an Au1200 generic file because
  * the parts chosen on another board may be different and may require
  * different timings.
  */
-#define NAND_T_H                       (18 >> 2)
-#define NAND_T_PUL                     (30 >> 2)
-#define NAND_T_SU                      (30 >> 2)
-#define NAND_T_WH                      (30 >> 2)
+#define NAND_T_H               (18 >> 2)
+#define NAND_T_PUL             (30 >> 2)
+#define NAND_T_SU              (30 >> 2)
+#define NAND_T_WH              (30 >> 2)
 
 /* Bitfield shift amounts */
 #define NAND_T_H_SHIFT         0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define NAND_T_SU_SHIFT                8
 #define NAND_T_WH_SHIFT                12
 
-#define NAND_TIMING    ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
-                       ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
-                       ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
-                       ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
-
+#define NAND_TIMING    (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                        ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                        ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                        ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
 
 /*
  * External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
        PB1200_INT_END          = PB1200_INT_BEGIN + 15
 };
 
-/* For drivers/pcmcia/au1000_db1x00.c */
-#define BOARD_PC0_INT PB1200_PC0_INT
-#define BOARD_PC1_INT PB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+/*
+ * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
+ */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
 
-/* Nand chip select */
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+       ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+#define BOARD_PC0_INT  PB1200_PC0_INT
+#define BOARD_PC1_INT  PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
+
+/* NAND chip select */
 #define NAND_CS 1
 
 #endif /* __ASM_PB1200_H */
-