[MIPS] Fix asm constraints for 'ins' instructions.

[linux-2.6-omap-h63xx.git] / include / asm-mips / bitops.h

diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 642724734eba3e2dee33fe01cdd7fb12e8648aa9..9a7274ba6a0b35a8e46d0b0ccb245bf2723f4545 100644 (file)
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                "2:     b       1b                                      \n"
                "       .previous                                       \n"
                : "=&r" (temp), "=m" (*m)
-               : "ir" (bit), "m" (*m), "r" (~0));
+               : "i" (bit), "m" (*m), "r" (~0));
 #endif /* CONFIG_CPU_MIPSR2 */
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                "2:     b       1b                                      \n"
                "       .previous                                       \n"
                : "=&r" (temp), "=m" (*m)
-               : "ir" (bit), "m" (*m));
+               : "i" (bit), "m" (*m));
 #endif /* CONFIG_CPU_MIPSR2 */
        } else if (cpu_has_llsc) {
                __asm__ __volatile__(
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                "2:     b       1b                                      \n"
                "       .previous                                       \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
-               : "ri" (bit), "m" (*m)
+               : "i" (bit), "m" (*m)
                : "memory");
 #endif
        } else if (cpu_has_llsc) {