[Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots.

[linux-2.6-omap-h63xx.git] / include / asm-blackfin / mach-bf548 / defBF54x_base.h

diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a48590c9c41965bb2210c08793f52e64e096f..08f90c21fe8a0f6538224f171853ea847177795d 100644 (file)
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
 #define                       TRP  0x3c0000   /* Pre charge-to-active command period */
 #define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
 #define                       TRC  0x3c000000 /* Active-to-active time */
+#define DDR_TRAS(x)            ((x<<22)&TRAS)  /* DDR tRAS = (1~15) cycles */
+#define DDR_TRP(x)             ((x<<18)&TRP)   /* DDR tRP = (1~15) cycles */
+#define DDR_TRC(x)             ((x<<26)&TRC)   /* DDR tRC = (1~15) cycles */
+#define DDR_TRFC(x)            ((x<<14)&TRFC)  /* DDR tRFC = (1~15) cycles */
+#define DDR_TREFI(x)           (x&TREFI)       /* DDR tRFC = (1~15) cycles */
 
 /* Bit masks for EBIU_DDRCTL1 */
 
 #define                      TRCD  0xf        /* Active-to-Read/write delay */
-#define                       MRD  0xf0       /* Mode register set to active */
+#define                      TMRD  0xf0       /* Mode register set to active */
 #define                       TWR  0x300      /* Write Recovery time */
 #define               DDRDATWIDTH  0x3000     /* DDR data width */
 #define                  EXTBANKS  0xc000     /* External banks */
 #define               DDRDEVWIDTH  0x30000    /* DDR device width */
 #define                DDRDEVSIZE  0xc0000    /* DDR device size */
-#define                     TWWTR  0xf0000000 /* Write-to-read delay */
+#define                      TWTR  0xf0000000 /* Write-to-read delay */
+#define DDR_TWTR(x)            ((x<<28)&TWTR)  /* DDR tWTR = (1~15) cycles */
+#define DDR_TMRD(x)            ((x<<4)&TMRD)   /* DDR tMRD = (1~15) cycles */
+#define DDR_TWR(x)             ((x<<8)&TWR)    /* DDR tWR = (1~15) cycles */
+#define DDR_TRCD(x)            (x&TRCD)        /* DDR tRCD = (1~15) cycles */
+#define DDR_DATWIDTH           0x2000          /* DDR data width */
+#define EXTBANK_1              0               /* 1 external bank */
+#define EXTBANK_2              0x4000          /* 2 external banks */
+#define DEVSZ_64               0x40000         /* DDR External Bank Size = 64MB */
+#define DEVSZ_128              0x80000         /* DDR External Bank Size = 128MB */
+#define DEVSZ_256              0xc0000         /* DDR External Bank Size = 256MB */
+#define DEVSZ_512              0               /* DDR External Bank Size = 512MB */
+#define DEVWD_4                        0               /* DDR Device Width = 4 Bits    */
+#define DEVWD_8                        0x10000         /* DDR Device Width = 8 Bits    */
+#define DEVWD_16               0x20000         /* DDR Device Width = 16 Bits    */
 
 /* Bit masks for EBIU_DDRCTL2 */
 
@@ -1790,6 +1809,10 @@
 #define                CASLATENCY  0x70       /* CAS latency */
 #define                  DLLRESET  0x100      /* DLL Reset */
 #define                      REGE  0x1000     /* Register mode enable */
+#define CL_1_5                 0x50            /* DDR CAS Latency = 1.5 cycles */
+#define CL_2                   0x20            /* DDR CAS Latency = 2 cycles */
+#define CL_2_5                 0x60            /* DDR CAS Latency = 2.5 cycles */
+#define CL_3                   0x30            /* DDR CAS Latency = 3 cycles */
 
 /* Bit masks for EBIU_DDRCTL3 */
 
@@ -2257,6 +2280,10 @@
 
 #define                      CSEL  0x30       /* Core Select */
 #define                      SSEL  0xf        /* System Select */
+#define                        CSEL_DIV1       0x0000  /* CCLK = VCO / 1 */
+#define                        CSEL_DIV2       0x0010  /* CCLK = VCO / 2 */
+#define                        CSEL_DIV4       0x0020  /* CCLK = VCO / 4 */
+#define                        CSEL_DIV8       0x0030  /* CCLK = VCO / 8 */
 
 /* Bit masks for PLL_CTL */