[ARM] 4090/2: avoid clash between PXA and SA1111 defines

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-pxa / pxa-regs.h

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index cff752f35230766554a28d9c7241704a9b5e37a0..a87165436b8c6a3fb694559737f0730ae82baf7f 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST  (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST  (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST     (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR   (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR   (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND   (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE (1 << 3)        /* Stop State (read-only) */
@@ -463,9 +463,6 @@
  * Serial Audio Controller
  */
 
-/* FIXME: This clash with SA1111 defines */
-#ifndef _ASM_ARCH_SA1111
-
 #define SACR0          __REG(0x40400000)  /* Global Control Register */
 #define SACR1          __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
 #define SASR0          __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
@@ -503,8 +500,6 @@
 #define SAIMR_RFS      (1 << 4)        /* Enable Rx FIFO Service Interrupt */
 #define SAIMR_TFS      (1 << 3)        /* Enable Tx FIFO Service Interrupt */
 
-#endif
-
 /*
  * AC97 Controller registers
  */
@@ -803,12 +798,11 @@
 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IECC   (1 << 31)       /* IntEn - Configuration Change */
-#define UDCISR1_IESOF  (1 << 30)       /* IntEn - Start of Frame */
-#define UDCISR1_IERU   (1 << 29)       /* IntEn - Resume */
-#define UDCISR1_IESU   (1 << 28)       /* IntEn - Suspend */
-#define UDCISR1_IERS   (1 << 27)       /* IntEn - Reset */
-
+#define UDCISR1_IRCC   (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF  (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU   (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU   (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS   (1 << 27)       /* IntReq - Reset */
 
 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
 #define UDCOTGICR      __REG(0x40600018) /* UDC On-The-Go interrupt control */
@@ -1627,7 +1621,7 @@
 #define SSCR0_RIM      (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 #define SSCR0_TUM      (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 #define SSCR0_FRDC     (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
 #define SSCR0_ADC      (1 << 30)       /* Audio clock select */
 #define SSCR0_MOD      (1 << 31)       /* Mode (normal or network) */
 #endif
@@ -1656,6 +1650,7 @@
 #define SSCR0_EDSS             (1 << 20)       /* Extended Data Size Select */
 
 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_TISSP            (1 << 4)        /* TI Sync Serial Protocol */
 #define SSCR0_PSP              (3 << 4)        /* PSP - Programmable Serial Protocol */
 #define SSCR1_TTELP            (1 << 31)       /* TXD Tristate Enable Last Phase */
 #define SSCR1_TTE              (1 << 30)       /* TXD Tristate Enable */